[paper] The advantages of p-GaN channel/Al2O3 gate insulator

Maria Ruzzarin,1, Carlo De Santi,1 Feng Yu,2 Muhammad Fahlesa Fatahilah,2 Klaas Strempel,2 Hutomo Suryo Wasisto,2 Andreas Waag,2 Gaudenzio Meneghesso,1 Enrico Zanoni,1

and Matteo Meneghini1

Highly stable threshold voltage in GaN nanowire FETs: The advantages of p-GaN channel/Al2O3 gate insulator

Appl. Phys. Lett. 117, 203501 (2020); 

DOI: 10.1063/5.0027922

Published Online: 16 November 2020

1 Department of Information Engineering, University of Padova, via Gradenigo 6/b, 35131 Padova, Italy
2 Institute of Semiconductor Technology (IHT) and Laboratory for Emerging Nanometrology (LENA), Technische Universitat Braunschweig, Langer Kamp 6a/b, 38106 Braunschweig, Germany

Abstract: We present an extensive investigation of the charge-trapping processes in vertical GaN nanowire FETs with a gate-all-around structure. Two sets of devices were investigated: Gen1 samples have unipolar (n-type) epitaxy, whereas Gen2 samples have a p-doped channel and an n-p-n gate stack. From experimental results, we demonstrate the superior performance of the transistor structure with a p-GaN channel/Al2O3 gate insulator in terms of dc performance. In addition, we demonstrate that Gen2 devices have highly stable threshold voltage, thus representing ideal devices for power electronic applications. Insight into the trapping processes in the two generations of devices was obtained by modeling the threshold voltage variations via differential rate equations.

Fig. a) The p-channel device (Gen2) comprises a 2.5 lm n-GaN buffer layer, a 0.5 lm p-GaN channel layer, 0.73 lm n-GaN and 0.5 lm n p-GaN as the top layer, and 25 nm-Al2O3 as the gate dielectric.

b) SEM images of a nanowire of the p-channel device (Gen2) and bird’s-eye view of vertically aligned n-p-n GaN nanowire (NW) arrays with top contacts.

Aknowledgement: This work was supported in part by NoveGaN (Univ. of Padova) through the STARS CoG Grants call. Ack prog. Eccellenza. This research was partly performed within project INTERNET OF THINGS: SVILUPPI METODOLOGICI, TECNOLOGICI E APPLICATIVI and co-funded (2018–2022) by the Italian Ministry of Education, Universities and Research (MIUR) under the aegis of the “Fondo per il finanziamento dei dipartimenti universitari di eccellenza” initiative (Law 232/2016). Financial support from the German Research Foundation (DFG) of 3D GaN project and the Lower Saxony Ministry of Science and Culture (N-MWK) of LENA-OptoSense group is highly acknowledged for the development of vertical GaN nanowire FETs.