[paper] Bendable non-silicon RISC-V microprocessor

Emre Ozer, Jedrzej Kufel, Shvetank Prakash2, Alireza Raisiardali, Olof Kindgren3, Ronald Wong,
Nelson Ng, Damien Jausseran, Feras Alkhalil, David Kong2, Gage Hills2, Richard Price
and Vijay Janapa Reddi2

Bendable non-silicon RISC-V microprocessor

Nature, vol. 634, pp. 341–346 (2024) 

DOI: 10.1038/s41586-024-07976-y

1 Pragmatic Semiconductor, Cambridge, UK
2 Harvard University, Cambridge, MA, USA

3 Qamcom, Karlstad, Sweden

Abstract: Semiconductors have already had a very profound effect on society, accelerating scientific research and driving greater connectivity. Future semiconductor hardware will open up new possibilities in quantum computing, artificial intelligence and edge computing, for applications such as cybersecurity and personalized healthcare. By nature of its ethos, open hardware provides opportunities for even greater collaboration and innovations across education, academic research and industry. Here we present Flex-RV, a 32-bit microprocessor based on an open RISC-V instruction set fabricated with indium gallium zinc oxide thin-film transistors on a flexible polyimide substrate, enabling an ultralow-cost bendable microprocessor. Flex-RV also integrates a programmable machine learning (ML) hardware accelerator inside the microprocessor and demonstrates new instructions to extend the RISC-V instruction set to run ML workloads. It is implemented, fabricated and demonstrated to operate at 60kHz consuming less than 6mW power. Its functionality when assembled onto a flexible printed circuit board is validated while executing programs under flat and tight bending conditions, achieving no worse than 4.3% performance variation on average. Flex-RV pioneers an era of sub-dollar open standard non-silicon 32-bit microprocessors and will democratize access to computing and unlock emerging applications in wearables, healthcare devices and smart packaging.

FIG a. Layout of the 9×6 mm2 test chip containing two Flex-RV microprocessors

b. The FlexPCB on which the die is assembled.

Data availability
Source data are provided with this paper.

Code availability

Serv is an open-source CPU, which is freely available at GitHub (https://github.com/olofk/serv). The source code of the test benchmarks, the changes made in the Serv CPU Verilog code, and the Verilog code of the ML hardware accelerator are available from the corresponding author upon request.