Showing posts with label
Logic gates
.
Show all posts
Showing posts with label
Logic gates
.
Show all posts
Apr 3, 2024
[paper] CMOS Technology for Analog Applications in High Energy Physics
›
Gianluca Traversi, Luigi Gaioni, Lodovico Ratti, Valerio Re and Elisa Riceputi Characterization of a 28 nm CMOS Technology for Analog Applic...
Jan 8, 2024
[paper] Polylogarithms in MOSFET Modeling
›
A. Ortiz-Conde and F. J. García-Sánchez Recent Applications of Polylogarithms in MOSFET Modeling 2023 IEEE 33rd International Conference on ...
Mar 8, 2023
[paper] Cryogenic Characteristics of InGaAs MOSFET
›
L. Södergren, P. Olausson and E. Lind Cryogenic Characteristics of InGaAs MOSFET in IEEE TED, vol. 70, no. 3, pp. 1226-1230, March 2023, DOI...
Nov 7, 2021
[paper] 3nm Nano-Sheet FETs
›
Etienne SICARD* and Lionel TROJMAN** Introducing 3-nm Nano-Sheet FET technology in Microwind hal-03377556: Submitted on 14 Oct 2021 *INSA...
1 comment:
Jun 1, 2020
[paper] Device Scaling for 3-nm Node and Beyond
›
Opportunities in Device Scaling for 3-nm Node and Beyond: FinFET Versus GAA-FET Versus UFET U. K. Das and T. K. Bhattacharyya in IEEE...
May 1, 2020
[paper] Physical Mechanisms of Reverse DIBL and NDR in FeFETs With Steep Subthreshold Swing
›
C. Jin, T. Saraya, T. Hiramoto and M. Kobayashi, in IEEE J-EDS, vol. 8, pp. 429-434, 2020 doi: 10.1109/JEDS.2020.2986345 Abstract - ...
›
Home
View web version
