[paper] Device Scaling for 3-nm Node and Beyond

Opportunities in Device Scaling for 3-nm Node and Beyond:

FinFET Versus GAA-FET Versus UFET

U. K. Das and T. K. Bhattacharyya

in IEEE TED, vol. 67, no. 6, pp. 2633-2638, June 2020, 

doi: 10.1109/TED.2020.2987139

Abstract: The performances of FinFET, gate-all-around (GAA) nanowire/nanosheet, and U-shaped FETs (UFETs) are studied targeting the 3-nm node (N3) and beyond CMOS dimensions. To accommodate a contacted gate pitch (CGP) of 32 nm and below, the gate length is scaled down to 14 nm and beyond. While going from 5-nm node (N5) to 3-nm node (N3) dimensions, the GAA-lateral nanosheet (LNS) shows 8% reduction in the effective drain current (I_eff) due to an enormous rise in short channel effects, such as subthreshold slope (SS) and drain-induced barrier lowering (DIBL). On the other hand, 5-nm diameter-based lateral nanowire shows an 80% rise in I_eff. Therefore, to enable future devices, we explored electrostatics and I_eff in FinFET, GAA-FET, and UFET architectures at a scaled dimension. The performances of both Si- and SiGe-based transistors are compared using an advanced TCAD device simulator.

Fig: Transistor architectures for future technologies. (a) FinFET device

(in {001} substrate plane, and sidewalls are in {110} planes) with crosssectional

fin channel (5 nm thin). (b) Fin is changed into a four-stacked

GAA-LNWs. (c) GAA- LNS having 20-nm width (W). (d) UFET structure.

Acknowledgment: The authors would like to thank Dr. Bidhan Pramanik, IIT Goa, India, Dr. KB Jinesh, IIST, Trivandrum, India, and Dr. Geert Eneman, IMEC, Leuven, Belgium, for their valuable technical support.

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9078841&isnumber=9098120