[book] Advanced Nanoscale MOSFET Architectures

Advanced Nanoscale MOSFET Architectures:

Current Trends and Future Perspectives

Kalyan Biswas, Angsuman Sarkar

John Wiley & Sons - Technology & Engineering (2024) 336 pages

ISBN: 978-1-394-18894-9

Comprehensive reference on the fundamental principles and basic physics dictating metal–oxide–semiconductor field-effect transistor (MOSFET) operation. Advanced Nanoscale MOSFET Architectures provides an in-depth review of modern metal–oxide–semiconductor field-effect transistor (MOSFET) device technologies and advancements, with information on their operation, various architectures, fabrication, materials, modeling and simulation methods, circuit applications, and other aspects related to nanoscale MOSFET technology. The text begins with an introduction to the foundational technology before moving on to describe challenges associated with the scaling of nanoscale devices. Other topics covered include device physics and operation, strain engineering for highly scaled MOSFETs, tunnel FET, graphene based field effect transistors, and more. The text also compares silicon bulk and devices, nanosheet transistors and introduces low-power circuit design using advanced MOSFETs.

Table of Contents:

[1] Emerging MOSFET Technologies; pp. 1

Kalyan Biswas and Angsuman Sarkar

[2] MOSFET: Device Physics and Operation; pp. 15

Ruthramurthy Balachandran, Savitesh M. Sharma, and Avtar Singh

[3] High-k Dielectrics in Next Generation VLSI/Mixed Signal Circuits; pp. 47

Asutosh Srivastava

[4] Consequential Effects of Trap Charges on Dielectric Defects for MU-G FET; pp. 61

Annada S. Lenka and Prasanna K. Sabu

[5] Strain Engineering for Highly Scaled MOSFETs; pp. 85

Chinmay K. Maiti, Taraprasanna Dash, Jhansirani Jena, and Eleena Mohapatra

[6] TCAD Analysis of Linearity Performance on Modified Ferroelectric Layer in FET Device with Spacer; pp. 113

Yash Pathak, Kajal Verma, Bansi Dhar Malhotra, and Rishu Chauzar

[7] Electrically Doped Nano Devices: A First Principle Paradigm; pp. 125

Debarato D. Ray, Pradipta Roy, and Debashis De

[8] Tunnel FET: Principles and Operations; pp. 143

Zahra Ahangari

[9] GaN Devices for Optoelectronics Applications; pp. 175

Nagarajan Mohankumar and Girish S. Mishra

[10] First Principles Theoretical Design on Graphene-Based Field-Effect Transistors; pp. 201

Yoshitaka Fujimoto

[11] Performance Analysis of Nanosheet Transistors for Analog ICs; pp. 221

Yogendra R Pundir, Arvind Bisht, and Pankaj K. Pal

[12] Low-Power Analog Amplifier Design using MOS Transistor in the Weak Inversion Mode; pp. 255

Soumya Pandit and Koyel Mukherjee

[13] Ultra-conductive Junctionless Tunnel FET-based Biosensor with Negative Capacitance; pp. 281

Palasri Dhar, Soumik Poddar, and Sunipa Roy

[14] Conclusion and Future Perspectives; pp. 301

Kalyan Biswas and Anqsuman Sarkar

[INDEX]; pp. 311

[Libre Silicon] Free Semiconductors For Everyone

Libre Silicon aims to take an active role in driving forward the change and reaching the objectives outlined before. Considering the fact that the free and open-source silicon ecosystem is growing explosively since the second half of the 2010s, many of the objectives are addressed already by others. In these cases, Libre Silicon wants to support their effort and adapt their results, without aiming at realizing the same goal differently, thus preventing the fragmentation of the ecosystem. In other topics, however, there is either no progress or the progress is not going in the desirable direction. In these cases, Libre Silicon takes a leading role, using the fullest possible extent of our expertise, commitment and resources. Our focus topics, without particular order, are the following:

• Develop free technology nodes, including manufacturing recipes, test structures, primitive devices, logic, padrings, analog and other libraries, characterization methodology, and PDK support.
• Drive the adoption of these nodes, by providing the necessary documentation, consulting and technical support. Libre Silicon also aims to set the example to follow by being early adopters of our own technology nodes, including the provision of actual manufacturing service.
• Elaborate novel business models to support the emergence of universal and affordable access to semiconductor technologies. This includes, among others, novel manufacturing operation organization concepts, throughput optimization for low-volume or high-volume production, and the introduction of new, connected manufacturing concepts and equipment.
• Develop novel manufacturing equipment enabling low-volume-capable, high-flexibility manufacturing, with primary focus on maskless lithographic technologies.

In addition to these efforts, Libre Silicon also aims at providing valuable contribution to the efforts of others with shared goals, including:

• Drive the necessary paradigm shift by advocating for free and open-source silicon solutions in real-life applications
• Support the education on IC design-related skillset by taking active role in the formation of training materials, supporting and organizing events like Hackathons or workshops and mentoring
• Support the development of EDA tools by advising on, and contributing to, the development of FOSS IC design software
• Increase the scope and quality of available free silicon IP libraries by developing our own libraries and contributing to the development of others

Libre Silicon roadmap is the following:

• Establishment of LibreSilicon Foundation in Europe
• Finish LS1U technology node (incl. SPICE parameter extraction)
• Development of ESD protection and pad cell library for LS1U
• Development of a maskless lithography stepper
• Tech Demo: LS555 (design, MLL fabrication, testing)
• Digital cell library for 1u MFS + digital tools (maybe parallel to LS1U/LS555)
• Tech demo II: 8-bit Arduino-compatible MCU
• To open Libresilicon Fabrication Service in EU
• Development of LS130 technology node (incl. MLL capability)
• Tech demo III: 130nm System-on-Chip
• Development of sub-100nm technology node (incl. MLL capability)
• Tech demo IV: SOC made on LibreSilicon runs GNU/Linux
• Successful tapeout of the Danube with Global Foundries. The first successful tapeout of the new autogenerated process verification wafer Danube River

Contact -> Lebre Silicon

[paper] Półprzewodnikowa rewolucja w domenie open source

Krzysztof Herman and Anna Sojka-Piotrowska

Półprzewodnikowa rewolucja w domenie open source

https://bit.ly/IHPOpenPDK

* IHP GmbH – Leibniz Institute for High Performance Microelectronics, Frankfurt (Oder), Niemcy

Abstract: Hasło „open source” kojarzy się większości osób przede wszystkim z oprogramowaniem tworzonym przez pasjonatów informatyki i udostępnianym za darmo ogólnoświatowej społeczności użytkowników. Nie mniej interesująca jest jednak grupa otwartych rozwiązań sprzętowych, czyli open source hardware – mało kto wie, że istnieją już bezpłatne pakiety oprogramowania przeznaczonego do projektowania układów scalonych, w tym nawet układów ASIC o paśmie rzędu setek GHz. Jeszcze większym zaskoczeniem może być fakt, że fabryki półprzewodników otwierają swoje podwoje także dla małych firm, partnerów akademickich, a nawet... odbiorców prywatnych! (czytaj dalej...)

Rys: Zestaw narzędzi open source do projektowania układów analogowych 

z uwzględnieniem pasma RF

Kontakt: dr Krzysztof Herman, dr Anna Sojka-Piotrowska

Ważne linki:

• IHP-Open-PDK https://github.com/IHP-GmbH/IHP-Open-PDK
• Free Silicon Foundation https://wiki.f-si.org/
• FOSSi Foundation https://fossi-foundation.org/
• eFabless  https://efabless.com
• Open Source Silicon @slack https://open-source-silicon.slack.com

[paper] Rapid MOSFET Threshold Voltage Testing

Michael H. Herman; Trenton T. Nguyen; Ken Wong; Jeff Johnson; Ben Morris

Rapid MOSFET Threshold Voltage Testing

for High Throughput Semiconductor Process Monitoring

2024 IEEE 36th International Conference on Microelectronic Test Structures (ICMTS)

Edinburgh, United Kingdom, 2024, pp. 1-6

doi : 10.1109/ICMTS59902.2024.10520252

* Parametric Test Group, Advantest America, San Jose, CA 95134 United States

Abstract : We describe a method for rapid MOSFET threshold voltage (Vt) measurement. Multiple spot Ids measurements are compared to stored reference data. Each spot measurement yields an independent Vt estimate, and these enable quality metric calculation. A Vt and quality metric can be measured within 7 msec, using two spot measurements. The method permits parallel MOS testing.

FIG : Reference Ids-Vgs Curve with Gm curveB2Q8 device 2N7002 NMOS Transistor
at Vds = 0.05 Gm(max) 0.02272 at Vgs 2.25V; Extrap tangent line at 1.8665V

[paper] CMOS strip sensors

Naomi Davis a, Jan-Hendrik Arling a, Marta Baselga d, Leena Diehl b f, Jochen Dingfelder c, Ingrid-Maria Gregor a, Marc Hauser b, Fabian Hügging c, Tomasz Hemperek c h, Karl Jakobs b, Michael Karagounis e, Roland Koppenhöfer b, Kevin Kröninger d, Fabian Lex b, Ulrich Parzefall b, Arturo Rodriguez b g, Birkan Sari d, Niels Sorgenfrei b f, Simon Spannagel a, Dennis Sperlich b, Tianyang Wang c, Jens Weingarten d, Iveta Zatocilova b

Characterisation and simulation of stitched CMOS strip sensors

Nuclear Instruments and Methods in Physics Research Section A:

Accelerators, Spectrometers, Detectors and Associated Equipment

Volume 1064, July 2024, 169407

DOI: 10.1016/j.nima.2024.169407

a Deutsches Elektronen Synchrotron DESY, Notkestr. 85, 22607 Hamburg, Germany
b Physikalisches Institut, University of Freiburg, Hermann-Herder-Straße 3, 79104 Freiburg, Germany
c Physikalisches Institut, University of Bonn, Nussallee 12, 53115 Bonn, Germany
d Physik E4, TU Dortmund, Otto-Hahn-Strasse 4a, 44227 Dortmund, Germany
e Fachhochschule Dortmund, Sonnenstraße 96, 44139 Dortmund, Germany
f CERN, Esplanade des Particules 1, 1211 Meyrin, Switzerland
g Littlefuse, Edisonstraße 15, 68623 Lampertheim, Germany
h DECTRIS AG, Täfernweg 1, 5405 Baden, Switzerland

Abstract : In high-energy physics, there is a need to investigate alternative silicon sensor concepts that offer cost-efficient, large-area coverage. Sensors based on CMOS imaging technology present such a silicon sensor concept for tracking detectors. The CMOS Strips project investigates passive CMOS strip sensors fabricated by LFoundry in a 150 nm technology. By employing the technique of stitching, two different strip sensor formats have been realised. The sensor performance is characterised based on measurements at the DESY II Test Beam Facility. The sensor response was simulated utilising Monte Carlo methods and electric fields provided by TCAD device simulations. This study shows that employing the stitching technique does not affect the hit detection efficiency. A first look at the electric field within the sensor and its impact on generated charge carriers is being discussed.

Fig : Schematic layout of the Regular (a) and Low Dose 30/55 (b) strip implant designs 

Acknowledgements : The measurements leading to these results have been performed at the Test Beam Facility at DESY Hamburg (Germany), a member of the Helmholtz Association (HGF).

[paper] Insights from Basilisk

Philippe Sauter∗, Thomas Benz∗, Paul Scheffler∗ , Frank K. Gurkaynak∗ , Luca Benini∗†

Insights from Basilisk:

Are Open-Source EDA Tools Ready for a Multi-Million-Gate, Linux-Booting RV64 SoC Design?

arXiv:2405.04257v2 [cs.AR] 8 May 2024

* Integrated Systems Laboratory, ETH Zurich, Switzerland
† Department of Electrical, Electronic, and Information Engineering, University of Bologna, Italy

Abstract: Designing complex, multi-million-gate application specific integrated circuits requires robust and mature electronic design automation (EDA) tools. We describe our efforts in enhancing the open-source Yosys+Openroad EDA flow to implement Basilisk, a fully open-source, Linux-booting RV64GC system-onchip (SoC) design. We analyze the quality-of-results impact of our enhancements to synthesis tools, interfaces between EDA tools, logic optimization scripts, and a newly open-sourced library of optimized arithmetic macro-operators. We also introduce a streamlined physical design flow with an improved power grid and cell placement integration. Our Basilisk SoC design was taped out in IHP’s open 130 nm technology. It achieves an operating frequency of 77 MHz (51 logic levels) under typical conditions, a 2.3 improvement compared to the baseline open-source EDA flow, while also reducing logic area by 1.6. Furthermore, tool runtime was reduced by 2.5, and peak RAM usage decreased by 2.9. Through collaboration with EDA tool developers and domain experts, Basilisk establishes solid "proof of existence" for a fully open-source EDA flow used in designing a competitive multi-million-gate digital SoC.

FIG: Layout files produced by running the original Iguana flow (a) and of Basilisk (b).

TABLE: KEY METRICS OF BASILISK

Logic area (NAND2)	1.1 MGE
Logic levelsa	51 LL
Technology	130 nm IHP
Operating frequency	77 MHz
SRAM memory	172 KiB (24 macros)
Chip / core area	39 mm / 21 mm
IO count	69

^aNumber of logic gates in the longest path

Acknowledgement: We thank Alan Mishchenko, Masahiro Fujita, Giovanni De Micheli, Andrea Costamagna, Alessandro Tempia Calvino, Osama Hammad Abdel Reheem, Matt Liberty, Martin Poviser, the Yosys team, Beat Muheim, and Zerun Jiang, for their valuable contributions to the research project. We further thank all contributors to the OS EDA tools.

We are deeply grateful to IHP for their generous support and providing us with the opportunity for an open-source tapeout of this scale.
This work was supported in part through the TRISTAN (101095947) project that received funding from the HORIZON KDT-JU programme

OSOC Initiative

One Student One Chip Initiative

Participators: Frontier System Laboratory, Architecture Laboratory

Status: Ongoing

The OSOC project guides students to design a tape-out open-source processor by combing EE with CS. It can help students improve their capacity of implementing software and hardware systems and learn how to design chips. Meanwhile, the project trains talents to be transferred to the high-performance processor "Xiangshan", open source EDA, open source IP and other teams and communities, which will continue to cultivate excellent reserve forces for advanced research and development of CS in China.

REF:

Institute of Computing Technology, Chinese Academy of Science　

No.6 Kexueyuan South Road Zhongguancun, Haidian District Beijing,China　

<https://acs.ict.ac.cn/english/projects_acs_en/202209/t20220927_46170.html>

[OpenUK] Open Manifesto

https://openuk.uk/openmanifesto/

February 6, 2024, launched at State of Open Con 24

Table of Contents:

1. Introduction

2. The status quo in the UK

3. Problems with the status quo

4. Three asks of a new UK Government

5. Vision: Giving back control through Open Source

6. Key benefits to UK economy by giving back control through Open Source

https://openuk.uk/stateofopen/

[paper] State Transitions in Autonomous Nonlinear Bistable Systems

Léopold Van Brandt and Jean-Charles Delvenne

Predicting State Transitions in Autonomous Nonlinear Bistable Systems

with Hidden Stochasticity

IEEE Control Systems Letters (L-CSS 2024)

* UCLouvain, Louvain-la-Neuve (B)

Abstract: Bistable autonomous systems can be found in many areas of science. When the intrinsic noise intensity is large, these systems exhibits stochastic transitions from one metastable steady state to another. In electronic bistable memories, these transitions are failures, usually simulated in a Monte-Carlo fashion at a high CPU-time price. Existing closed form formulas, relying on near-stable-steady-state approximations of the nonlinear system dynamics to estimate the mean transition time, have turned out inaccurate. Our contribution is twofold. From a unidimensional stochastic model of overdamped autonomous systems, we propose an extended Eyring-Kramers analytical formula accounting for both nonlinear drift and state-dependent white noise variance, rigorously derived from Itô stochastic calculus. We also adapt it to practical system engineering situations where the intrinsic noise sources are hidden and can only be inferred from the fluctuations of observables measured in steady states. First numerical trials on an industrial electronic case study suggest that our approximate prediction formula achieve remarkable accuracy, outperforming previous non-Monte-Carlo approaches.

Fig: (a) SRAM bitcell retaining a logical 0 or 1 encoded on two complementary node voltages (v2 and v1) as low and high levels VL and VH. The retained state is stabilised by a feedback loop implemented by two cross-coupled inverters. An inverter is a nonlinear time-invariant system producing a high VH (resp. low VL) output when its input is maintained at constant low VL (resp. high VH), yet with internal dynamics and intrinsic noise.

(b) Transient noise simulation at supply voltage VDD = 70 mV (adapted from [1]). Intrinsic noise-induced stochastic state transitions (bit flips VL ↔ VH) are observed. VM denotes the threshold voltage corresponding to the unstable state. For the illustrated case, the bistable system is symmetrical in the sense that two inverters are identical, making the two steady states equiprobable and the transitions VL ↔ VH rates equal.

Acknowledgements: The work has been partially supported by the Research Project "Thermodynamics of Circuits for Computation" of the National Fund for Scientific

Research (FNRS) of Belgium.

[Latch-Up] IHP Open Source PDK

IHP Open Source PDK:

Announcement, Setup, Current State and Experiences, and look ahead

Frank Vater, IHP Frankfurt (Oder), Germany

Latch-Up 2024 video

Abstract: Main focus of this talk is the SG13G2 Open Source PDK for IHP 130nm BiCMOS technology. The current state of our activities will be given for the analogue as well as for the digital PDK including design flow with open source tools. Some more details on first experiences for schematic driven design, simulation, layout, DRC and LVS will be pointed out. Furthermore, already known challenges analogue and digital design flow and open issues on open source tool chain will be addressed. The talk will be closed with a road map for future work.

Latch-Up: a weekend of presentations and networking for the open source silicon community, much like its European sister conference ORConf.

Produced by NDV: @nextdayvideo
OpenHardware Sat Apr 20 16:20:00 2024 at b45r230

[paper] Compact Model of IDG BEOL Transistor for Capacitorless Memory

Lihua Xu, Kaifei Chen, Zhi Li, Yue Zhao, Lingfei Wang and Ling LiPhysics-Based 

Compact Model of Independent Dual-Gate BEOL-Transistors

for Reliable Capacitorless Memory

in IEEE Journal of the Electron Devices Society

DOI: 10.1109/JEDS.2024.3393418  

School of Microelectronics, University of Science and Technology of China, Hefei (CN)
State Key Lab of FTIC, Institute of Microelectronics of Chinese Academy of Sciences, Beijing (CN)
University of Chinese Academy of Sciences, Beijing (CN)

Abstract: Capacitorless DRAM architectures based on Back End-of-Line (BEOL)-transistors are promising for long retention, high-density and low-power 3D DRAM solutions due to its low leakage, operational flexibility, and monolithic integration capability. Different from classical silicon-based devices, in-depth studies on the performances of nanoscale multi gate transistors (e.g., a-InGaZnO-FET) are still barely conducted for physical description, due to the complicated multi-gating principle, finite-size effects on transport, increased variation sources and enlarged parasitic effect. Hence, high-performance multi-nanoscale (down to ~ 50 nm) dual-gate a-IGZO transistors are fabricated, and a physical compact model is developed based on the surface potential for dual-gated coupling and the disordered transport with finite-size-correction. The short channel behaviors on sub-threshold swing, mobility and threshold voltage are investigated, and contact effects are validated by the transfer-line method (TLM). Regarding the specific challenge of dual-gate alignment, possible misalignment and parasitic effects on multi-device fluctuations are important of large-scale circuit design and analyzed by TCAD simulations. Besides, the bias-temperature instability (BTI) has been comprehensively investigated. In awareness of the above effects, this model bridges fabrication-based material properties and structural parameters, assisting in a threshold fluctuation resistant operation scheme for capacitorless multi-bit memory, showing a great potential in future monolithic integration circuit design using BEOL-transistor.

Fig: (a) Schematic illustration of the IDG a-IGZO FETs with a thickness of ~5nm. (b) Agreement between analytical and numerical results of back gate surface potentials at different VDS with errors in the inset. VTG & VBG denotes DG synchronized-sweep with the same voltage.

Acknowledgements: This work was supported in part by National key research and development program (Grant Nos. 2021YFB3600704), the National Natural Science Foundation of China (Grant Nos. 62274178, 92264204), CAS Interdisciplinary Innovation Team [JCTD-2022-07].

[IC Design] Single Photon Counting ASIC for Synchrotron Applications

Ultra-Fast Single Photon Counting ASIC for Fast Synchrotron Applications

Dr hab. inż Piotr Kmon

AGH University, Cracow, Poland

European Synchrotron Radiation Facility (ESRF), Grenoble, France

Abstract: The SPHIRD (Small Pixel High Rate photon counting Detector) project is an R&D study to investigate how far the photon counting X-ray hybrid pixel detector technology can go, regarding photon rate and spatial resolution. A goal was to boost by 30 times the count-rate capabilities of existing detectors of similar pixel size. SPHIRD targets that figure by designing fast front end electronics, by including pile-up compensation techniques in the pixel logic, and by implementing smaller pixels. Each pixel contains fast front-end analog electronics (pulse width is only 18ns) with base-line holder (BLH), a set of discriminators (with offset trimming blocks), ripple counters, and digital blocks. The pixel architecture allows also for operation in conventional mode (STDC) and with different pulse pile-up compensation methods (these are voltage and time based methods named VDIS, TDIS, and FPHC respectively).

Fig: Schematic idea of the recording channel and the chip photo with mounted detector

Technology: TSMC 40nm GP; Die Size: 3.2mm x 3.5mm

Acknowledgements: The chip design was realized by P. Grybos, R. Kleczek, P. Otfinowski, and P. Kmon (AGH) while synchrotron experiments were conducted by P. Fajarado, D. Magalhaes and M. Raut.

References
[1] P. Grybos,et.al., “SPHIRD–Single Photon Counting Pixel Readout ASIC With Pulse Pile-Up Compensation Methods”, IEEE IEEE Transactions on Circuits and Systems--II: Express Briefs, vol. 70, no. 9, 2023, p. 3248-3252.
[2] D. Magalhaes et al., Very High Rate X-ray Photon Counting 2D Detectors with Small Pixels: the SPHIRD Project. 2022 IEEE NSS-MIC-RTSD Conference Proceedings.

[CNM25] Academic Process Design Kit

The aim of this academic process design kit (APDK) is to introduce circuit designers to the top-down design methodology of mixed-signal full-custom integrated circuits (ICs) in CMOS technologies. For this purpose, the following freely available electronic design automation (EDA) tools are proposed for both the schematic and the physical IC design. The APDK incorporates all the required technological information for the simple 2.5um 1P2M PiP CMOS technology (CNM25) from IMB-CNM(CSIC). Anyway, this APDK can be easily customized to extend its coverage to more complex CMOS technologies.

News 2024.04.09:

APDK release version 2024_04_09
+ Update to Glade 6.x series (Qt6)
+ Screenshots

REF: Poster at IEEE ISCAS 2017 in Baltimore, MD, USA.

CONTACT: 

Francesc Serra-Graells

www.cnm.es/users/pserra

tel: +34 93 594 77 00

fax: +34 93 580 02 67

IMB-CNM (CSIC)

Campus UAB Bellaterra

08193 Cerdanyola del Vallès, SPAIN