Talk from W. Grabinski about #compact models at #QuantiAmony #winter #school

Talk from W. Grabinski about #compact models at #QuantiAmony #winter #school. Also very to see that he uses the image (then nice transistor on the yellow page in the middle) made in Device Modeling Group as an example. #cmos #simulations #modelling #semi https://t.co/cqBLzSY2Xq https://t.co/Ry7lH8UThK

— Wladek Grabinski (@wladek60) Feb 28, 2023

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from Twitter https://twitter.com/wladek60

February 28, 2023 at 02:25PM
via IFTTT

[paper] ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors

ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation

Alessandro Ottaviano1, Robert Balas1, Giovanni Bambini2, Antonio del Vecchio2, Maicol Ciani2, Davide Rossi2, Luca Benini1,2 and Andrea Bartolini2

DOI: 10.21203/rs.3.rs-2525734/v1

1 Integrated Systems Laboratory, ETH Zurich, Gloriastrasse 35, Zurich, 8092, Switzerland.
2 DEI, University of Bologna, Viale Del Risorgimento 2, Bologna, 40136, Italy

Abstract: High-Performance Computing (HPC) processors are nowadays integrated Cyber-Physical Systems demanding complex and high-bandwidth closed-loop power and thermal control strategies. To efficiently satisfy real-time multi-input multi-output (MIMO) optimal power requirements, high-end processors integrate an on-die power controller system (PCS). While traditional PCSs are based on a simple microcontroller (MCU)-class core, more scalable and flexible PCS architectures are required to support advanced MIMO control algorithms for managing the ever-increasing number of cores, power states, and process, voltage, and temperature variability. This paper presents ControlPULP, an open-source, HW/SW RISC-V parallel PCS platform consisting of a single-core MCU with fast interrupt handling coupled with a scalable multicore programmable cluster accelerator and a specialized DMA engine for the parallel acceleration of real-time power management policies. ControlPULP relies on FreeRTOS to schedule a reactive power control firmware (PCF) application layer. We demonstrate ControlPULP in a power management use-case targeting a next-generation 72-core HPC processor. We first show that the multicore cluster accelerates the PCF, achieving 4.9x speedup compared to single-core execution, enabling more advanced power management algorithms within the control hyper-period at a shallow area overhead, about 0.1% the area of a modern HPC CPU die. We then assess the PCS and PCF by designing an FPGA based, closed-loop emulation framework that leverages the heterogeneous SoCs paradigm, achieving DVFS tracking with a mean deviation within 3% the plant’s thermal design power (TDP) against a software-equivalent model-in-the-loop approach. Finally, we show that the proposed PCF compares favorably with an industry grade control algorithm under computational-intensive workloads.

• https://github.com/Arm-software/SCP-firmware
• https://github.com/open-power
• https://github.com/pulp-platform/control-pulp 
• https://github.com/openhwgroup/cv32e40p
• https://github.com/pulp-platform/clic
• https://github.com/EEESlab/examon
• https://buildroot.org/

FIG: ControlPULP hardware architecture. On the left, the manager domain with the manager core and surrounding peripherals. On the right, the cluster domain accelerator with the eight cores (workers)

 

[paper] Framework for FPGA Emulation of IC Designs

S. Herbst, G. Rutsch, W. Ecker and M. Horowitz

An Open-Source Framework for FPGA Emulation of Analog/Mixed-Signal Integrated Circuit Designs

in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

vol. 41, no. 7, pp. 2223-2236, July 2022

DOI: 10.1109/TCAD.2021.3102516

Abstract: This article presents an open-source framework for emulating mixed-signal chip designs on a field-programmable gate array (FPGA). It includes a Python-based synthesizable model generator for mixed-signal blocks (msdsl), a fixed-point and floating-point synthesizable SystemVerilog library for representing real numbers (svreal), and a Python-based tool that generates emulator control infrastructure and automates the FPGA build process (anasymod). The framework includes features for efficiently modeling analog dynamics, nonlinearity, and noise, often making use of compile-time caching to reduce the required computational resources of the FPGA. We demonstrate the framework’s generality by discussing three applications: 1) a high-speed link receiver (DragonPHY); 2) a firmware-controlled flyback converter; and 3) an NFC-powered chip. Our framework makes it easy to emulate these systems, while providing runtimes 2–3 orders of magnitude faster than CPU simulations with real-number functional models. FOSS framework, depicted in Fig. 1, consists of three tools: 1) msdsl ; 2) svreal; and 3) anasymod. All three tools released as open source can be installed either from GitHub or by using the Python package manager (pip).

FIG: Overview of FOSS AMS emulation framework. Analog models are described in Python and compiled into synthesizable SystemVerilog using msdsl, leveraging svreal to implement real-number operations. anasymod then wraps emulator control infrastructure around the DUT and automates EDA tools to produce an FPGA bitstream.

[review] SOI devices and their basic properties

Rudenko, T. E., A. N. Nazarov, and V. S. Lysenko

The advancement of silicon-on-insulator (SOI) devices and their basic properties

Semiconductor Physics, Quantum Electronics & Optoelectronics 23, no. 3 (2020)

DOI: 10.15407/spqeo23.03.227

* V. Lashkaryov Institute of Semiconductor Physics, NAS of Ukraine, 45, prospect Nauky, 03680 Kyiv, Ukraine

Abstract. Silicon-on-insulator (SOI) is the most promising present-day silicon technology. The use of SOI provides significant benefits over traditional bulk silicon technology in fabrication of many integrated circuits (ICs), and in particular, complementary metal-oxide-semiconductor (CMOS) ICs. It also allows extending the miniaturization of CMOS devices into the nanometer region. In this review paper, we briefly describe evolution of SOI technology and its main areas of application. The basic technological methods for fabrication of SOI wafers are presented. The principal advantages of SOI devices over bulk silicon devices are described. The types of SOI metal-oxide-semiconductor field-effect transistors (MOSFETs) and their basic electrical properties are considered. Keywords: silicon-on-insulator (SOI), metal-oxide-semiconductor field-effect transistor (MOSFET), multiple-gate transistor, ultra-thin-body SOI transistor, fully-depleted SOI transistor, interface coupling.

FIG: Equivalent capacitance circuit of the long-channel bulk / PD SOI MOSFET (a), and FD SOI MOSFET (b). Subthreshold characteristics of FD SOI MOSFET and bulk / PD SOI MOSFET (c).

[paper] Fast and Expandable ANN-Based Extraction

Jeong, HyunJoon, SangMin Woo, JinYoung Choi, HyungMin Cho, Yohan Kim,

Jeong-Taek Kong, and SoYoung Kim

Fast and Expandable ANN-Based Compact Model and Parameter Extraction for Emerging Transistors IEEE Journal of the Electron Devices Society (2023)

DOI 10.1109/JEDS.2023.3246477

Abstract: In this paper, we present a fast and expandable artificial neural network (ANN)-based compact model and parameter extraction flow to replace the existing complicated compact model implementation and model parameter extraction (MPE) method. In addition to nanosheet FETs (NSFETs), our published ANN based compact modeling framework is easily extended to negative capacitance NSFETs (NC-NSFETs), which are attracting attention as next-generation devices. Each device is designed using a technology computer-aided design (TCAD) simulator. Using device structure parameters, temperature, and channel doping depth as input variables, we construct a dataset of electrical properties used for machine learning (ML)-based modeling. The accuracy of predicting device electrical characteristics with the proposed ANN-based compact model is less than a 1% error compared to TCAD, and simulation results of digital and analog circuits using the proposed compact model show less than a 3% error. This allows the ANN-based modeling framework to achieve accurate DC, AC, and transient simulations without restrictions on device technology. In particular, temperature and process variables such as channel doping depth, which are not defined in the compact model parameters, are easily added to the previously presented five key parameters. Instead of conventional complex compact modeling and MPE work, we propose a method to create fast, accurate, flexible, and expandable ML-based Verilog-A SPICE models with design technology co-optimization (DTCO) capabilities.

Fig A: Conventional model parameter extraction flow

Fig B: The proposed ANN-based model parameter extraction flow

Acknowledgments: We thank the reviewers for improving the contents of the paper. This work was supported by an Institute of Information & communications Technology Planning & Evaluation (IITP) grant funded by the Korean government (MSIT) (No.2021-0- 00754, Software Systems for AI Semiconductor Design) and by a National Research Foundation of Korea grant funded by the Korean government (MISP) (NRF-2020R1A2C1011831). The EDA tool was supported by the IC Design Education Center (IDEC), Korea

[ElectronicsB2B ] #TSMC To Build Second #semi #Foundry In #Japan https://t.co/v8BTcb97vh https://t.co/rvvCz2MTgY

[ElectronicsB2B ] #TSMC To Build Second #semi #Foundry In #Japan https://t.co/v8BTcb97vh https://t.co/rvvCz2MTgY

— Wladek Grabinski (@wladek60) Feb 24, 2023

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from Twitter https://twitter.com/wladek60

February 24, 2023 at 05:17PM
via IFTTT

[C4P] FSiC 2023

The 2023 Free Silicon Conference (FSiC)

will take place in Paris (Sorbonne)

on July 10-12, 2023 (Monday to Wednesday)

This event will build on top of the past FSiC2019 and FSiC2022 editions. The conference will connect experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference will cover the full spectrum of the design process, from system architecture, to layout and verification. After the daily talks, the discussion will continue until late in an informal and relaxed atmosphere.

Participation to the conference is free of charge, but the attendance must be reserved per email at fsic2023 'at' f-si.org. Details will be announced on this page and over the mastodon channel. The slides and the video recordings of the talks will be published on our website.

Discussion topics of the 2023 Free Silicon Conference (FSiC) 

• High-level design
• Hardware security
• On-going FOSS silicon projects
• Memories
• Foundries and free PDKs
• Transistor Compact/SPICE/Verlog-A modeling
• Place-and-route tools
• Parasitic extraction
• Design rule checking
• Schematic editors
• Photonics
• Sustainability

Submission: For proposing a talk, please submit a title and a short summary at
fsic2023 'at' f-si.org.

FSiC Organizing Committee

Review of cryogenic neuromorphic hardware

Md Mazharul Islam¹, Shamiul Alam¹, Md Shafayat Hossain³, Kaushik Roy³, 

and Ahmedullah Aziz¹,

A review of cryogenic neuromorphic hardware

Journal of Applied Physics 133, no. 7 (2023): 070701

DOI: 10.1063/5.0133515

1Department of Electrical Engineering and Computer Science, University of Tennessee, Knoxville, Tennessee 37996, USA
2Department of Physics, Princeton University, Princeton, New Jersey 08544, USA
3Department of Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana 47906, USA

ABSTRACT: The revolution in artificial intelligence (AI) brings up an enormous storage and data processing requirement. Large power consumption and hardware overhead have become the main challenges for building next-generation AI hardware. To mitigate this, neuromorphic computing has drawn immense attention due to its excellent capability for data processing with very low power consumption. While relentless research has been underway for years to minimize the power consumption in neuromorphic hardware, we are still a long way off from reaching the energy efficiency of the human brain. Furthermore, design complexity and process variation hinder the large-scale implementation of current neuromorphic platforms. Recently, the concept of implementing neuromorphic computing systems in cryogenic temperature has garnered intense interest thanks to their excellent speed and power metric. Several cryogenic devices can be engineered to work as neuromorphic primitives with ultra-low demand for power. Here, we comprehensively review the cryogenic neuromorphic hardware. We classify the existing cryogenic neuromorphic hardware into several hierarchical categories and sketch a comparative analysis based on key performance metrics. Our analysis concisely describes the operation of the associated circuit topology and outlines the advantages and challenges encountered by the state-of-the-art technology platforms. Finally, we provide insight to circumvent these challenges for the future progression of research.

FIG: (a) Biological neuron connected with multiple neurons through synapses. The inset shows the transportation of the neurotransmitter. (b) Electronic model of a neuromorphic system showing the integration of weighted spikes. (c) Several conventional hardware platforms. (d) Several cryogenic platforms for neuromorphic hardware. (e) Input spikes (Vin), corresponding membrane potential (Vmem), and output spike (Vout) of a leaky integrating and fire (LIF) neuron. An output spike is generated after Vmem crosses the threshold voltage (Vth). (f) Switching speed and switching energy comparison of conventional and cryogenic hardware.

[Book] More-than-Moore Devices and Integration for Semiconductors

More-than-Moore Devices and Integration

for Semiconductors

Editors: Francesca Iacopi and Francis Balestra

Publisher: Springer Cham

DOI: 10.1007/978-3-031-21610-7

This book provides readers with a comprehensive, state-of-the-art reference for miniaturized More-than-Moore systems with a broad range of functionalities that can be added to 3D microsystems, including flexible electronics, metasurfaces and power sources. The book also includes examples of applications for brain-computer interfaces and event-driven imaging systems.

• Provides a comprehensive, state-of-the-art reference for miniaturized More-than-Moore systems;
• Covers functionalities to add to 3D microsystems, including flexible electronics, metasurfaces and power sources;
• Includes current applications, such as brain-computer interfaces, event - driven imaging and edge computing.

Table of contents (7 chapters)

• Front Matter Pages i-xiv
• Energy Harvesters and Power Management Pages 1-45
  Michail E. Kiziroglou, Eric M. Yeatman
• SiC and GaN Power Devices Pages 47-104
  Konstantinos Zekentes, Victor Veliadis, Sei-Hyung Ryu, Konstantin Vasilevskiy, Spyridon Pavlidis, Arash Salemi et al.
• Flexible and Printed Electronics Pages 105-125
  Benjamin Iñiguez
• Terahertz Metasurfaces, Metawaveguides, and Applications Pages 127-156
  Wendy S. L. Lee, Shaghik Atakaramians, Withawat Withayachumnankul
• Mechanical Robustness of Patterned Structures and Failure Mechanisms
  Ehrenfried Zschech, Maria Reyes Elizalde Pages 157-189
• Neuromorphic Computing for Compact LiDAR Systems Pages 191-240
  Dennis Delic, Saeed Afshar
• Integrated Sensing Devices for Brain-Computer Interfaces Pages 241-258
  Tien-Thong Nguyen Do, Ngoc My Hanh Duong, Chin-Teng Lin

Acknowledgements: We would like to thank the following colleagues for their help in peer-reviewing this book’s material: Dr. Yang Yang and Dr. Diep Nguyen (University of Technology Sydney, Australia); Prof. Xuan-Tu Tran (Vietnam National University Hanoi), Prof. Gustavo Ardila and Prof. Pascal Xavier (University Grenoble Alpes, France); and Prof. Edwige Bano (Grenoble INP, France). FI would also like to acknowledge support from the Australian Research Council Centre of Excellence in Transformative MetaOptical Systems (TMOS, CE200100010).

Francesca Iacopi, Ultimo, NSW, Australia 

Francis Balestra, Grenoble, France 

2022 SSCS Outstanding Chapter Award

Our SSCS Switzerland Chapter, with Prof. Taekwang Jang as its Chair, was recognized as the outstanding chapter of the year 2022. Dear my fellow Swiss colleagues, the chapter offering the best lectures, seminars, and social events is right at your next door, and you can enjoy them by joining the IEEE SSCS members here.

[C4P] T-ED Special Issue

Call for Papers - Special Issue on "Wide and Ultrawide Band Gap Semiconductor Devices for RF and Power Applications."

The Special Issue of the IEEE Transactions on Electron Devices (T-ED) will report the most advanced and recent results in the field of wide and ultrawide bandgap semiconductor materials and devices, including papers focused on material fabrication, device processing, reliability investigation, device modeling, thermal aspects, and system-related results.

Submission deadline: 31 August 2023
Publication date: February 2024

Submit papers today: https://bit.ly/3fESTgZ

Guest Editors: 

Prof. Matteo Meneghini, University of Padova, Italy 

Prof. Patrick Fay, University of Notre Dame, USA 

Prof. Digbijoy Nath, IISC Bangalore 

Prof. Geok Ing Ng, Nanyang Technical University, Singapore 

Prof. Junxia Shi, University of Illinois, Chicago 

Prof. Shyh-Chiang Shen, Georgia Tech. 

FOSS Verilog-A Models Repository

Dietmar Warning, ngspice team, has announced his new github project VA-Models repository 
<https://github.com/dwarning/VA-Models>

These Verilog-A model code repository is a compilation of the most important models in the state of public FOSS availability. The intention is to have one place for model access and a platform for discussion and integration into simulators.

At the moment, the models will be compiled by script with openVAF and checked with ngspice version 39. Code changes are introduced only for convergence support or to fulfill Verilog-A language standard requirements. Model equations are untouched. But I am open to integrate code modifications for other compiler/simulator companions as far they are inline with actual LRM 2.4. Simple test case are provided, mainly to show general functionality of the compiled models. 

Don't hesitate to contact Dietmar Warning, ngspice team, if there is something wrong, especially in kind of legal aspects. All the contributions are welcome.

How many semiconductor talents are there?

How many semiconductor talents are there? SMIC’s response: It is good to have sufficient reserves for employee benefits–Fast Technology–Technology Changes the Future https://t.co/rQsQls9EOd #semi https://t.co/793nEsMLcF

— Wladek Grabinski (@wladek60) Feb 12, 2023

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February 12, 2023 at 07:36PM
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#Wolfspeed to Build 200-mm #SiC #Wafer #Fab in Germany

#Wolfspeed to Build 200-mm #SiC #Wafer #Fab in Germany https://t.co/WZIzzETJ44 #semi https://t.co/RY58nMQ2B1

— Wladek Grabinski (@wladek60) Feb 9, 2023

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from Twitter https://twitter.com/wladek60

February 09, 2023 at 08:46PM
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[Compact Model Coalition] Advanced SPICE model for ESD diodes https://t.co/n83vRcQhhK #semi https://t.co/PIuhcqVLw2

[Compact Model Coalition] Advanced SPICE model for ESD diodes https://t.co/n83vRcQhhK #semi https://t.co/PIuhcqVLw2

— Wladek Grabinski (@wladek60) Feb 9, 2023

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February 09, 2023 at 06:07PM
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[C4P] RISC-V Summit Europe

On 5-9th June, in Barcelona, RISC-V Summit Europe brings together developers, architects, technical decision and policy makers from across European RISC-V ecosystem. Attendees from academia, research, SMEs, industry and open source communities will gather to exchange knowledge, ideas, technologies, and research shaping the future of RISC-V computing.

The event will include a single track of keynotes, invited and selected talks alongside an exhibition showcasing the latest developments across industry and research including technology demonstrations and poster sessions.

RISC-V Summit Europe is an opportunity not to be missed, come to Barcelona from 5-9th June 2023 to be part of the new wave of European computing innovation!

Call for Submissions

RISC-V Summit Europe brings together developers, architects, technical decision and policy makers from across the European RISC-V ecosystem. Attendees from academia, research, SMEs, industry, and open source communities will come together to exchange knowledge, ideas, technologies, and research shaping the future of RISC-V computing in Europe.

The event will have a single track of keynotes, invited and selected talks alongside an exhibition showcasing the latest developments across industry and research, including technology demonstrations and poster sessions. We invite blind submissions related to RISC-V addressing the following technical topics of interest:

    Automotive
    Cloud computing
    Compilation and code optimization
    Embedded systems, IoT, edge computing
    Hardware/software co-design
    High-performance computing
    Open EDA tools
    Open-source hardware and open silicon
    Operating system and software ecosystem
    RISC-V related educational activities
    RISC-V ISA extensions
    Systems-on-Chip, including processor cores, accelerators, peripherals
    Security and functional safety
    Verification
    Any other topic related to RISC-V and open hardware

We also welcome non-blind submissions related to:

    Commercial applications for real world deployment
    Policies, strategies, business and industry trends
    Publicly funded projects presentations and/or results

Important dates:

    Abstract submissions hard deadline: Monday, March 13th, 2023, AOE.
    Author notifications: Monday, April 24th, 2023, AOE.
    Final abstract version, de-anonymized, deadline: Thursday, Monday May 1st, 2023, AOE.
    Final slides and poster deadline: Thursday, June 1st, 2023, AOE.
    RISC-V Summit Europe: 5-9 June, 2023, Barcelona.
 

 

 

 

[Hisayo Momose] My Journey as a Researcher in the Semiconductor Field

 

Hisayo Mosmose's Story 

Read Hisayo Momose's article from the IEEE EDS January Newsletter, "My Journey as a Researcher in the Semiconductor Field."

Dr. Momose has more than 30 years of experience in research and development at Toshiba Corporation, Japan. She is a recipient of several awards and honors, and has authored or co-authored nearly 200 papers published in technical journals and conference proceedings [read more...]

#IEEE #EDS #ElectronDevices #WiEDS #womeinengineering #semiconductors
 

 

 

[paper] OpenSpike: An OpenRAM SNN Accelerator

Farhad Modaresi¹, Matthew Guthaus², and Jason K. Eshraghian³
OpenSpike: An OpenRAM SNN Accelerator
arXiv:2302.01015v1 [cs.AR] 2 Feb 2023

1) Dept. of Electrical Engineering Allameh Mohaddes Nouri University Nur, Mazandaran, Iran
2) Dept. of Computer Science and Engineering, UC Santa Cruz Santa Cruz, CA, United States
3) Dept. of Electrical and Computer Engineering, UC Santa Cruz Santa Cruz, CA, United States

Abstract: This paper presents a spiking neural network (SNN) accelerator made using fully open-source EDA tools, process design kit (PDK), and memory macros synthesized using Open- RAM. The chip is taped out in the 130 nm SkyWater process and integrates over 1 million synaptic weights, and offers a reprogrammable architecture. It operates at a clock speed of 40 MHz, a supply of 1.8 V, uses a PicoRV32 core for control, and occupies an area of 33.3 mm2. The throughput of the accelerator is 48,262 images per second with a wallclock time of 20.72 μs, at 56.8 GOPS/W. The spiking neurons use hysteresis to provide an adaptive threshold (i.e., a Schmitt trigger) which can reduce state instability. This results in high performing SNNs across a range of benchmarks that remain competitive with state-of-the-art, full precision SNNs.

The design is open sourced and available online: https://github.com/sfmth/OpenSpike

Fig: OpenSpike core - system architecture and data flow

 

 

[C4P] IEEE LAEDC 2023

On behalf of the Organizing Committee of  IEEE 2023 Latin American Electron Devices Conference (LAEDC) we want to invite you to the next edition of our conference. It will take place in Puebla, Mexico from July 3-5, 2023.

The conference is growing rapidly with worldwide participation and will cover key topics in the field of electronic devices. The main objective of LAEDC is to bring together specialists from all fields related to electronic devices, it will also be aimed at students and young researchers. This event is financially sponsored by IEEE Electron Devices Society (EDS). We are sure that thanks to your significant achievements and contributions, your attendance will significantly increase the value of our conference and motivate research groups and young generations in the field of electronic devices. Please note that discounted registration will be available until June 17, 2023.

Please consider submitting a full paper to our conference proceedings no later than March 31th and engage with our audience and participants while visiting one of the most lively and historic cities in Mexico. For more information, please visit our web site and do not hesitate to contact us 

Sincerely

[C4P] EDISON 22 Conference

22nd International Conference on Electron Dynamics
in Semiconductors, Optoelectronics and Nanostructures
(EDISON 22)

to be held 14 – 18 August 2023 in Münster, Germany

Abstract submission:
The abstract submission site is now open. Prospective authors are invited to submit a one-page abstract in pdf-format via the conference website

https://edison22.uni-muenster.de/ .

Templates for the abstracts in LaTeX, Word and OpenDocument format can be downloaded from this site. Please follow the guidelines given in the templates. For the submission please follow the upload link on the website.

The deadline for the submission of abstracts will be 15 March 2023.

About the conference:
EDISON 22 follows a series of conferences formerly named Hot Carriers in Semiconductors and since 2009 running under the name EDISON. It is dedicated to the latest progress in the field of fundamental physics and applications of nonequilibrium classical and quantum carrier dynamics in semiconductors, optoelectronic devices and nanostructures. Main topics of the conference are:

- Nonequilibrium electrical and thermal transport in bulk, nanostructures and devices
- Terahertz phenomena in semiconductor materials and devices
- Mesoscopic phenomena in nanostructures
- Electrical and optical properties of 2D materials and their heterostructures
- Carrier dynamics and ultra-fast optical phenomena
- Coherent carrier dynamics for quantum technologies
- Semiconductor-based spintronics
- Electronic properties of topological materials
- Carrier dynamics in organic materials
- Charge dynamics in energy conversion and energy harvesting processes
- Fluctuations and noise in nonequilibrium carrier dynamics
- Interaction of charges with plasmonic, phononic and mechanical excitations

Confirmed invited speakers:
- Satoshi Iwamoto (University of Tokyo, Japan)
- Takashi Nakajima (RIKEN, Saitama, Japan)
- Andrea Secchi (CNR Istituto Nanoscienze, Modena, Italy)
- Ian R. Sellers (University of Oklahoma, USA)
- Oren Tal (Weizmann Institute of Science, Rehovot, Israel)
- Klaas-Jan Tielrooij (Eindhoven University of Technology, Netherlands)
- Yanko Todorov (École Normale Supérieure, Paris, France)
- Stephan Winnerl (Helmholtz-Zentrum Dresden Rossendorf, Germany)
- Ilaria Zardo (University of Basel, Switzerland)

For more information see the attached flyer and visit the EDISON 22 website. Please direct any questions or comments to edison22@uni-muenster.de .

We are looking forward to seeing you in Münster.

With best regards from the organizers,

Tilmann Kuhn (Chair)
Rudolf Bratschitsch (Co-Chair)
Hubert Krenner (Co-Chair)
Ursula Wurstbauer (Co-Chair)


If you do not wish to receive further emails regarding EDISON conferences, please send us a notice or reply to this email with the subject: unsubscribe.

How to #make your own #laptop computer using #Pi400

How to #make your own #laptop computer using #Raspberry #Pi400 https://t.co/rHihUhUAbI #semi https://t.co/k4lwAPPOAg

— Wladek Grabinski (@wladek60) Feb 7, 2023

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February 07, 2023 at 12:11PM
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#STM linked to #Indian #fab project as former #NXP exec appointed

#STM linked to #Indian #fab project as former #NXP exec appointed https://t.co/7LxfjqFVch #semi

— Wladek Grabinski (@wladek60) Feb 7, 2023

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February 07, 2023 at 11:23AM
via IFTTT

#10top #Semi Companies To Watch In #2023

[https://t.co/PI5zxrQkzJ] #10top #Semi Companies To Watch In #2023 1. AMD 2. Ampere Computing 3. ARM 4. Astera Labs 5. Cerebras Systems 6. Intel 7. Cerebras Systems 8. Qualcomm 9. Tenstorrent 10. Ventana Micro Systems https://t.co/nnGtTzRPuh

— Wladek Grabinski (@wladek60) Feb 3, 2023

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February 03, 2023 at 04:57PM
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#Google sets up #semi #IC engineering team in #Taiwan

#Google sets up #semi #IC engineering team in #Taiwan, sources say https://t.co/CEisxrlWh0 https://t.co/Lop5cqQ57Y

— Wladek Grabinski (@wladek60) Feb 3, 2023

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February 03, 2023 at 02:21PM
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Paradigm shift - smaller, better, faster: #imec presents #chip scaling roadmap

Paradigm shift - smaller, better, faster: #imec presents #chip scaling roadmap https://t.co/Nlay0RmnbM #semi https://t.co/KbTqTb9VPY

— Wladek Grabinski (@wladek60) Feb 3, 2023

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February 03, 2023 at 10:33AM
via IFTTT

[paper] Tang, X., Shen, H., Zhao, S. et al. #Flexible #brain–#computer #interfaces

[paper] Tang, X., Shen, H., Zhao, S. et al. #Flexible #brain–#computer #interfaces. Nat Electron (2023). https://t.co/7ei1DjEDv4 https://t.co/ku9TzOgvgX #semi https://t.co/061ERANncp

— Wladek Grabinski (@wladek60) Feb 3, 2023

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February 03, 2023 at 08:30AM
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RT @UMichECE: This chip by @SaliganeMehdi is part of the #opensource #semi hardware movement to democratize #IC design, a movement supported by many, including @NIST and @Google Read more: https://t.co/BVufryP3j2 https://t.co/Pkvocdinma

RT @UMichECE: This chip by @SaliganeMehdi is part of the #opensource #semi hardware movement to democratize #IC design, a movement supported by many, including @NIST and @Google Read more: https://t.co/BVufryP3j2 https://t.co/Pkvocdinma

— Wladek Grabinski (@wladek60) Feb 2, 2023

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February 02, 2023 at 11:55AM
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