Review of cryogenic neuromorphic hardware

Md Mazharul Islam¹, Shamiul Alam¹, Md Shafayat Hossain³, Kaushik Roy³, 

and Ahmedullah Aziz¹,

A review of cryogenic neuromorphic hardware

Journal of Applied Physics 133, no. 7 (2023): 070701

DOI: 10.1063/5.0133515

1Department of Electrical Engineering and Computer Science, University of Tennessee, Knoxville, Tennessee 37996, USA
2Department of Physics, Princeton University, Princeton, New Jersey 08544, USA
3Department of Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana 47906, USA

ABSTRACT: The revolution in artificial intelligence (AI) brings up an enormous storage and data processing requirement. Large power consumption and hardware overhead have become the main challenges for building next-generation AI hardware. To mitigate this, neuromorphic computing has drawn immense attention due to its excellent capability for data processing with very low power consumption. While relentless research has been underway for years to minimize the power consumption in neuromorphic hardware, we are still a long way off from reaching the energy efficiency of the human brain. Furthermore, design complexity and process variation hinder the large-scale implementation of current neuromorphic platforms. Recently, the concept of implementing neuromorphic computing systems in cryogenic temperature has garnered intense interest thanks to their excellent speed and power metric. Several cryogenic devices can be engineered to work as neuromorphic primitives with ultra-low demand for power. Here, we comprehensively review the cryogenic neuromorphic hardware. We classify the existing cryogenic neuromorphic hardware into several hierarchical categories and sketch a comparative analysis based on key performance metrics. Our analysis concisely describes the operation of the associated circuit topology and outlines the advantages and challenges encountered by the state-of-the-art technology platforms. Finally, we provide insight to circumvent these challenges for the future progression of research.

FIG: (a) Biological neuron connected with multiple neurons through synapses. The inset shows the transportation of the neurotransmitter. (b) Electronic model of a neuromorphic system showing the integration of weighted spikes. (c) Several conventional hardware platforms. (d) Several cryogenic platforms for neuromorphic hardware. (e) Input spikes (Vin), corresponding membrane potential (Vmem), and output spike (Vout) of a leaky integrating and fire (LIF) neuron. An output spike is generated after Vmem crosses the threshold voltage (Vth). (f) Switching speed and switching energy comparison of conventional and cryogenic hardware.