[paper] OpenSpike: An OpenRAM SNN Accelerator

Farhad Modaresi¹, Matthew Guthaus², and Jason K. Eshraghian³
OpenSpike: An OpenRAM SNN Accelerator
arXiv:2302.01015v1 [cs.AR] 2 Feb 2023

1) Dept. of Electrical Engineering Allameh Mohaddes Nouri University Nur, Mazandaran, Iran
2) Dept. of Computer Science and Engineering, UC Santa Cruz Santa Cruz, CA, United States
3) Dept. of Electrical and Computer Engineering, UC Santa Cruz Santa Cruz, CA, United States

Abstract: This paper presents a spiking neural network (SNN) accelerator made using fully open-source EDA tools, process design kit (PDK), and memory macros synthesized using Open- RAM. The chip is taped out in the 130 nm SkyWater process and integrates over 1 million synaptic weights, and offers a reprogrammable architecture. It operates at a clock speed of 40 MHz, a supply of 1.8 V, uses a PicoRV32 core for control, and occupies an area of 33.3 mm2. The throughput of the accelerator is 48,262 images per second with a wallclock time of 20.72 μs, at 56.8 GOPS/W. The spiking neurons use hysteresis to provide an adaptive threshold (i.e., a Schmitt trigger) which can reduce state instability. This results in high performing SNNs across a range of benchmarks that remain competitive with state-of-the-art, full precision SNNs.

The design is open sourced and available online: https://github.com/sfmth/OpenSpike

Fig: OpenSpike core - system architecture and data flow