[paper] Framework for FPGA Emulation of IC Designs

S. Herbst, G. Rutsch, W. Ecker and M. Horowitz

An Open-Source Framework for FPGA Emulation of Analog/Mixed-Signal Integrated Circuit Designs

in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

vol. 41, no. 7, pp. 2223-2236, July 2022

DOI: 10.1109/TCAD.2021.3102516

Abstract: This article presents an open-source framework for emulating mixed-signal chip designs on a field-programmable gate array (FPGA). It includes a Python-based synthesizable model generator for mixed-signal blocks (msdsl), a fixed-point and floating-point synthesizable SystemVerilog library for representing real numbers (svreal), and a Python-based tool that generates emulator control infrastructure and automates the FPGA build process (anasymod). The framework includes features for efficiently modeling analog dynamics, nonlinearity, and noise, often making use of compile-time caching to reduce the required computational resources of the FPGA. We demonstrate the framework’s generality by discussing three applications: 1) a high-speed link receiver (DragonPHY); 2) a firmware-controlled flyback converter; and 3) an NFC-powered chip. Our framework makes it easy to emulate these systems, while providing runtimes 2–3 orders of magnitude faster than CPU simulations with real-number functional models. FOSS framework, depicted in Fig. 1, consists of three tools: 1) msdsl ; 2) svreal; and 3) anasymod. All three tools released as open source can be installed either from GitHub or by using the Python package manager (pip).

FIG: Overview of FOSS AMS emulation framework. Analog models are described in Python and compiled into synthesizable SystemVerilog using msdsl, leveraging svreal to implement real-number operations. anasymod then wraps emulator control infrastructure around the DUT and automates EDA tools to produce an FPGA bitstream.