FOSS CAD research is in the spotlight

The conference paper "FOSS as an efficient tool for extraction of MOSFET compact model parameters" reached 20 reads at the researchgate.net

FOSS as an efficient tool for extraction of MOSFET compact model parameters

D. Tomaszewski, G. Głuszko, M. Brinson, V. Kuznetsov and W. Grabinski

MIXDES 2016, Lodz, pp. 68-73.

doi: 10.1109/MIXDES.2016.7529702

Abstract—A GNU Octave – based application for device-level compact model evaluation and parameter extraction has been developed. The applications main features are as follows: experimental I-V data importing, generating input data for different circuit simulation programs, running the simulation program to calculate I-V characteristics of the specified models, calculating model misfit and its sensitivity to selected parameter variation, and the comparison of experimental and simulated characteristics. Measured I-V data stored by different measurement systems are accepted. Circuit simulations may be done with Ngspice, Qucs and LTSpiceIV. Selected aspects of the application are presented and discussed. 

Ken Shirriff Takes Us Inside the IC, For Fun https://t.co/QScTdhgFXV #papers

Ken Shirriff Takes Us Inside the IC, For Fun https://t.co/QScTdhgFXV #papers

— Wladek Grabinski (@wladek60) December 27, 2016

from Twitter https://twitter.com/wladek60

December 27, 2016 at 09:24PM
via IFTTT

J-EDS Comes of Age https://t.co/4HNl9cQhzh #papers

J-EDS Comes of Age https://t.co/4HNl9cQhzh #papers

— Wladek Grabinski (@wladek60) December 27, 2016

from Twitter https://twitter.com/wladek60

December 27, 2016 at 01:07PM
via IFTTT

Special Issue of Solid-State Electronics, dedicated to EUROSOI-ULIS 2016 https://t.co/fFD9GehZEP #papers #feedly

Special Issue of Solid-State Electronics, dedicated to EUROSOI-ULIS 2016 https://t.co/fFD9GehZEP #papers #feedly

— Wladek Grabinski (@wladek60) December 25, 2016

from Twitter https://twitter.com/wladek60

December 25, 2016 at 09:14PM
via IFTTT

[paper] Analysis and Compact Modeling of Negative Capacitance Transistor

Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current
and Negative Output Differential Resistance
Part II: Model Validation

Girish Pahwa, Student Member, IEEE, Tapas Dutta, Member, IEEE, Amit Agarwal,
Sourabh Khandelwal, Member, IEEE, Sayeef Salahuddin, SM IEEE,
Chenming Hu, IEEE Fellow, and Yogesh Singh Chauhan, SM IEEE 

in IEEE Transactions on Electron Devices, vol. 63, no. 12, pp. 4986-4992, Dec. 2016

doi: 10.1109/TED.2016.2614436

Abstract: In this paper, we show a validation of our compact model for negative capacitance FET (NCFET) presented in Part I. The model is thoroughly validated with the TCAD simulations with respect to ferroelectric thickness scaling and temperature effects. Interestingly, we find that an NCFET with PZT ferroelectric of a large thickness provides a negative output differential resistance in addition to an expected high ON current and a sub-60 mV/decade subthreshold swing. The model is also tested for the Gummel symmetry and its transient capabilities are highlighted through a ring oscillator circuit simulation.

[read more at IEEE Xplore]

[Call for Papers] ESSCIRC–ESSDERC 2017

September 11-14, 2017

LEUVEN - Belgium
www.esscirc-essderc2017.org

ESSCIRC–ESSDERC annual Conference is the most important European forum for the presentation and discussion of recent advances in solid-state devices and circuits: MAKE SURE TO BE PART OF IT!

CALL for PAPERS

GUESS WHO IS COMING!

LOCAL SCIENTIFIC SECRETARIAT
​Cor Claeys (imec, BE) | General Chair
Chantal Deboes (imec, BE) | ESSDERC Chair
Danielle Vermetten (KU Leuven, BE) | ESSCIRC Chair

ORGANIZERS   

TECHNICAL CO-SPONSORSHIP
ESSDERC FINANCIAL SPONSOR 
ESSCIRC FINANCIAL SPONSOR 
DIAMOND SPONSOR  

ORGANIZING SECRETARIAT: Sistema Congressi s.r.l. 

[online] Verilog-AMS Quick Reference and Tutorials

Verilog-AMS is a hardware description language that can model both analog and digital systems. The official description of the Verilog-AMS language is contained in the Verilog-AMS Language Reference Manual.

This site is designed to be your quick reference guide for Verilog-A and Verilog-AMS. The reference material is not complete at this point, but is still quite usable. Over time the reference material should fill out and be supplemented with useful application notes and annotated models that will help you learn to use Verilog-A/MS more effectively. The emphasis is very much on analog and mixed-signal modeling. If you are looking for information on synthesis or the obscure corners of the Verilog language, you must look elsewhere

• Verilog-AMS Quick Reference
• The Verilog-AMS Language
• Verilog-AMS Tutorials
• Glossary
• Index
• Search

Both Ken & Henry at Designer’s Guide Consulting aim to make www.VerilogAMS.com your everyday source for information on Verilog-A/MS. Please take a look around, and tell your friends and co-workers. If you have questions about Verilog-AMS, feel free to ask them on
the forum at designers-guide.org.

QUCS mentioned in IEEE-EDL paper

Jacopo Iannacci, Fondazione Bruno Kessler (FBK), Trento, Italy, has recently published an article in the IEEE Electron Device Letters (EDL) where he used and explicitly mentioned the QUCS, FOSS CAD/EDA simulator:

RF-MEMS Technology for Future Mobile and High-Frequency Applications:

Reconfigurable 8-Bit Power Attenuator Tested up to 110 GHz

J. Iannacci, M. Huhn, C. Tschoban and H. Pötter

in IEEE EDL, vol. 37, no. 12, pp. 1646-1649, Dec. 2016.

Abstract: In this letter, we present and test—to the best of our knowledge, for the first time—, an 8-bit (256-state) reconfigurable RF-MEMS attenuator, from 10 MHz up to 110 GHz, realized in the CMM-FBK technology. Resistive loads, in series and shunt configuration, are selectively inserted on the RF line by means of electrostatic MEMS ohmic switches. The network exhibits several attenuation levels in the range of −10/−45 dB that are rather flat up to 50 GHz, and a certain number of configurations with VSWR smaller than 4 from nearly dc up to 110 GHz, and better than 2 on a frequency span of ~80 GHz.

doi: 10.1109/LED.2016.2623328

[read more: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7726036&isnumber=7739309]

Top #opensource #conference picks for #2017 https://t.co/nJzg2bSbpq #papers

Top #opensource #conference picks for #2017 https://t.co/nJzg2bSbpq #papers

— Wladek Grabinski (@wladek60) December 14, 2016

from Twitter https://twitter.com/wladek60

December 14, 2016 at 10:37AM
via IFTTT

[paper] A surface potential large signal model for AlGaN/GaN HEMTs

A surface potential large signal model for AlGaN/GaN HEMTs

Q. Wu, Y. Xu, Z. Wen, Y. Wang and R. Xu

2016 11th EuMIC, London, UK, 2016, pp. 349-352

doi: 10.1109/EuMIC.2016.7777562

Abstract: This paper presents an accurate analytical surface-potential-based compact model for AlGaN/GaN HEMTs for SPICE-like circuit simulation. Considering the important energy level E₀, an easy-implemented analytical continuous expression for the fermi level position E_f was deduced to obtain the surface potential (SP) φ_s. Then analytical core models for intrinsic charge and drain current are derived based on φ_s. The model has been implemented in Agilent ADS by using symbolic defined device. Excellent agreement of DC I-V, fundamental output power, power added efficiency and gain is obtained for the first time compared with measurement results. Moreover, the effect of physical parameter such as the barrier thickness d on device characteristic is researched on the basic of this model. The results show that the proposed physical based model can be useful for technological parameters analysis and optimization of process.

[read more: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7777562&isnumber=7777458]

Writing a science/tech book, is it that hard?

Writing a science/tech book, is it that hard?

As a microwave engineer Errikos Lourandakis, PhD, a senior R&D engineer at Helic Inc., started with RF device characterization while working on his PhD. He got fascinated about it and gradually devoted much of his time in the lab (see his lab pic below), though RF and Microwave Measurements were just a vehicle for microwave circuit design that was his actual PhD topic. After 10+ years in academia and industry, recently he has also published his new book "On-Wafer Microwave Measurements and De-embedding"

Errikos' RF and mm-Wave Measurement Lab

Is it worth it? [read more...]

[Fellowship] Physics Based Modeling Simulation and Electrical Characterization

Physics Based Modeling Simulation and Electrical Characterization 

of Quantum Effects in Multigate MOSFETs

[DRDO Fellowship]

Dr. Vimala Palanichamy is looking for Junior Research Fellowship (INR 25000 Stipend per Month) for this project funded by Defense Research and Development Organization (DRDO), Government of India. Please refer below advertisement for applying for Junior Research Fellowship for working on the project: 

http://dayanandasagar.edu/dsce/images/pdf/Advertisement_for_JRF.pdf

The #efabless $15,000 #Design #Challenge https://t.co/OV5sjnfSxm #papers

The #efabless $15,000 #Design #Challenge https://t.co/OV5sjnfSxm #papers

— Wladek Grabinski (@wladek60) November 30, 2016

from Twitter https://twitter.com/wladek60

November 30, 2016 at 01:17PM
via IFTTT

Investigation of Gate Direct-Current and Fluctuations in Organic p-Type Thin-Film Transistors #papers https://t.co/IS3MAiWqZY

Investigation of Gate Direct-Current and Fluctuations in Organic p-Type Thin-Film Transistors #papers https://t.co/IS3MAiWqZY

— Wladek Grabinski (@wladek60) November 29, 2016

from Twitter https://twitter.com/wladek60

November 29, 2016 at 02:51PM
via IFTTT

#Opensource #lab-on-a-board costs $29 https://t.co/cJIQPpDgvG #software #feedly #papers

#Opensource #lab-on-a-board costs $29 https://t.co/cJIQPpDgvG #software #feedly #papers

— Wladek Grabinski (@wladek60) November 26, 2016

from Twitter https://twitter.com/wladek60

November 26, 2016 at 08:25PM
via IFTTT

[paper] RESURF Model and Electrical Characteristics of Finger-Type STI Drain Extended MOS Transistors

RESURF Model and Electrical Characteristics of Finger-Type STI Drain Extended MOS Transistors
H. C. Tsai, R. H. Liou and C. Lien
IEEE Transactions on Electron Devices
vol. 63, no. 12, pp. 4603-4609, Dec. 2016

Abstract: Finger-type shallow trench isolation (finger STI) drain extended MOS transistors are fabricated and its electrical characteristics is studied. Polyplate on a finger STI served as a reduced surface field is adopted to enhance breakdown voltage (BV) by reducing the effective doping concentration of the drain extension (DE) finger. The conformal mapping method, which relates the reduction of the doping concentration to the width (z_o) of the DE finger, the gap (z_d) between the polyplate and the DE finger, and the STI depth (y_s), is used to estimate the reduction of the doping concentration theoretically. Based on this reduced doping concentration, a BV model is derived. The predictions of this model agree very well with the experimental data.

Keywords: Conformal mapping, Doping, Electric breakdown, MOS devices, Semiconductor process modeling, Silicon, Transistors, Drain extended MOS (DEMOS), Lateral double Diffused MOS (LDMOS), poly field plate, reduced surface field (RESURF)

doi: 10.1109/TED.2016.2605504
[read more...]

[paper] Small-Signal Characterization and Modeling of 55 nm SiGe BiCMOS HBT up to 325 GHz

Small-Signal Characterization and Modeling of 55 nm SiGe BiCMOS HBT up to 325GHz

Marina Deng^a, Thomas Quémerais^b, Simon Bouvot^a, ^b, Daniel Gloria^b, Pascal Chevalier^b

Sylvie Lépilliet^a, François Danneville^a, Gilles Dambrine^a

^aIEMN UMR CNRS 8520, University of Lille, Avenue Poincaré, CS60069, 

59652 Villeneuve-d’Ascq Cedex, France

^bSTMicroelectronics, 850 rue Jean Monnet, 38926 Crolles, France

Highlights

• The SiGe HBT full S-parameters from 250MHz to 325GHz under multiple bias conditions are presented for the first time.
• Standard calibration and de-embedding techniques are used and remained valid up to 325GHz thanks to a reduction of the test structures dimensions.
• A simple and accurate small-signal electrical model was extracted and compared with measurements up to 325GHz.

Received 19 September 2016, Revised 18 November 2016, Accepted 21 November 2016, Available online 22 November 2016 [read more...]

http://dx.doi.org/10.1016/j.sse.2016.11.012

2016 IEDM Tutorials

2016 International Electron Devices Meeting Tutorials

The tutorials are in their sixth year and are 90 minute stand-alone presentations on specialized topics taught by world-class experts. These tutorials provide a brief introduction to their respective fields, and facilitate understanding of the technical sessions. The tutorial sessions will take place on Saturday, Dec.3, 2016. Three tutorials are given in parallel in two time slots, at 2:45 p.m.and 4:30 p.m. respectively.

Topics presented at 2:45pm - 4:15pm:

• The Struggle to Keep Scaling BEOL, and What We Can Do Next
  Rod Augur, Distinguished Member of the Technical Staff, GlobalFoundries
• Physical Characterization of Advanced Devices
  Robert Wallace, Univ. Texas at Dallas
• Spinelectronics: From Basic Phenomena to Magnetoresistive Memory (MRAM) Applications
  Bernard Dieny, Chief Scientist, Spintec CEA

Topics presented at 4:30pm - 6:00pm:

• Electronic Circuits and Architectures for Neuromorphic Computing Platforms
  Giacomo Indiveri, Univ. of Zurich and ETH Zurich
• Present and Future of FEOL Reliability—from Dielectric Trap Properties to Reliable Circuit Operation
  Ben Kaczer, Principal Scientist, IMEC
• Embedded Systems and Innovative Technologies for IoT Applications
  Ali Keshavarzi, Vice President of R&D, Cypress Semiconductor

Register for the IEDM tutorials here: http://ieee-iedm.org/onsite-registration-center/online-registration/

EKV302.00 in Cadence MMSIM 14.10

EKV302.00 is available in Cadence MMSIM 14.10. The new version can be accessed through version control parameter. It includes several enhancements, new flicker noise model and new operating point features.

INFOS 2017 in Potsdam, Germany

20th Conference on “Insulating Films on Semiconductors” 

INFOS 2017

June 27th – 30th, 2017 in Potsdam, Germany

The INFOS conference is a prestigious biennial event which brings together electrical engineers, technologists, materials scientists, device physics and chemists from Europe and around the world to debate the latest development in thin insulating film technology and identify as well as address challenges ahead in this highly diversifying field [read more...]

Conference Topics:

• High-k dielectrics, metal gate materials and SiO2 for future scaling
• Gate stack materials for high mobility substrates (Ge, SiGe, GaN, III-V)
• Stacked dielectrics for non-volatile memory (flash, nc-Si)
• Dielectrics for resistive switching memories and spin memories
• Dielectrics for DRAM and MIM
• Low-k dielectrics
• Semiconductors on insulators
• Dielectrics for 2D materials, nanowires, 2D devices and carbon-based devices
• Surface cleaning technologies
• Physics and chemistry of dielectrics and defects
• Characterization techniques for dielectrics and interfaces
• Electrical reliability, leakage and modelling
• Modelling of atomic structure of dielectrics, interfaces and thin films
• Topological insulators
• Ferroelectrics and functional oxides
• Dielectrics and thin films for TFT, amorphous or organic devices and photovoltaics
• Dielectrics for photonics and sensing

Creating A PCB In Everything: KiCad, Part 1 https://t.co/gSqz7GGbnE #todo #feedly #papers

Creating A PCB In Everything: KiCad, Part 1 https://t.co/gSqz7GGbnE #todo #feedly #papers

— Wladek Grabinski (@wladek60) November 17, 2016

from Twitter https://twitter.com/wladek60

November 17, 2016 at 11:23PM
via IFTTT

Open Source License Compliance bei Embedded-Systemen

Open Source License Compliance bei Embedded-Systemen 

( Kompaktseminar, ESE Kongress 2016, in Sindelfingen )

Referent: Dr. Till Jaeger, JBB Rechtsanwälte

Zeit: 28.11.16 09:00-12:30

Abstract: When using Linux and other open source software (OSS), the license terms of the GPL and other open source licenses must be adhered to. As license violations lead directly to copyright infringements, appropriate compliance measures are necessary. The compact seminar presents the essential requirements for a compliance process based on the OpenChain Initiative. OpenChain aims at an international standard for suppliers using OSS in your products.

Outline:

1. What is Open Source Software?
2. How does the open source license model work?
3. Legal consequences of violation of OSS license terms
4. How is it ensured that the use of OSS is known and which licensing conditions are affected?
5. The Copyleft (1): When must self-development be released again as OSS?
6. Copyleft (2): Verification of license compatibility between different OSS licenses
7. Process to comply with sales obligations (for example, source code offer, co-delivery license texts)
8. Methods of quality control

[read more...]

National Workshop on Advanced Nanoscale Device Design Using TCAD

The National Workshop on Advanced Nanoscale Device Design Using Technology Computer-Aided Design (TCAD) was organized by the IEEE SolidState Circuits Society (SSCS) College of Engineering Chengannur, India Chapter. The workshop was held 28 December 2015 through 1 January 2016 as a three-day tutorial and two-day handson session. The event was graced with the presence of distinguished lecturers from top institutions in India, including Prof. Yogesh S. Chouhan from IIT Kanpur delivering the keynote talk. The workshop attracted approximately 150 participants from 15 reputable academic institutions. People from industry and also attended the event.

The coordinators were proud to present a successful workshop as one of the first events since the formation of the Chapter. The event was funded by the SSCS extra subsidy program. The feedback received from the attendees was very positive. Each participant received a certificate during the closing ceremony of the event. The five-day workshop came to an end by the heartfelt vote of thanks by Nisha Kuruvilla, with a motto “This is just the beginning.” [read more...]

[paper] Analysis of aging effects - From transistor to system level

Analysis of aging effects - From transistor to system level

Maike Taddiken*, Nico Hellwege, Nils Heidmann, Dagmar Peters-Drolshagen, Steffen Paul

Institute of Electrodynamics and Microelectronics,
University of Bremen, Otto-Hahn-Allee 1, Bremen 28359,Germany

ABSTRACT: Due to shrinking feature sizes in integrated circuits, additional reliability effects have to be considered which influence the functionality of the system. These effects can either result from the manufacturing process or external influences during the lifetime such as radiation and temperature. Additionally, modern technology nodes are affected by time-dependent degradation i.e. aging. Due to the age-dependent degradation of a circuit, processes on the atomic scale of the semiconductor material lead to charges in the oxide silicon interface of CMOS devices, altering the performance parameters of the device and subsequently the behavior of the circuit. With the continuous downscaling of modern semiconductor technologies, the impact of these atomic scale processes affecting the overall system characteristics becomes more and more critical. Therefore, aging effects need to be assessed during the design phase and actions have to be taken guaranteeing the correct system functionality throughout a system’s lifetime. This work presents methods to investigate the influence of age-dependent degradation as well as process variability on different levels. An operating-point dependent sizing methodology based on the gm/ID method extended to incorporate aging, which aims at developing aging-resistent circuits is presented. The basic idea of the gm/ID sizing method is the dependence of the operating point of a MOS transistor on the state of inversion in the channel, its strong relation to circuit performance and the possibility to calculate transistor dimensions.The inversion coefficient IC is a fundamental metric within the gm/ID method and numerically represents the inversion level of a MOS device formally described in the EKV MOS model. Additionally, the sensitivity of circuit performances in regard to aging can be determined. In order to investigate the reliability of a complex system on behavioral level, a modeling method to represent the performance of system components in dependence of aging and process variability is introduced. [read more...]

ICNF 2017: 2nd Call for Papers

24th International Conference on Noise and Fluctuations (ICNF 2017) 

20-23 of June 2017 in Vilnius, Lithuania

We would like to invite you to submit your abstracts. For submission of the abstracts, please, REGISTER and go to the Abstract submission site. Instruction for authors and templates for abstract preparation can be found and downloaded  at the Conference website: http://www.icnf2017.ff.vu.lt/paper-submission/instructions-for-authors
Deadline of the abstract submission is 22 January, 2017

Please also keep in mind ICNF2017 important dates:

• Abstract submission deadline: 22 January, 2017
• Notification of acceptance deadline: 27 February, 2017
• Full paper submission deadline:27 March, 2017
• Early bird registration: 19 April, 2017
• Conference: 20-23 June, 2017

Please share this information to your colleagues and those who might be interested in ICNF 2017.

For more information visit the Conference website: http://www.icnf2017.ff.vu.lt/
or contact us: icnf2017@ff.vu.lt

Looking forward to meeting you in Vilnius.

With best regards,
Sandra Pralgauskaitė and Paulius Sakalas - Organizing Committee Chairs

[mos-ak] [Final Program] 9th International MOS-AK Workshop Berkeley DEC.7, 2016

9th International MOS-AK Workshop  

  Berkeley December 7, 2016 
    Final Workshop Program 

 
Together with the MOS-AK workshop host, Prof. Jaijeet Roychowdhury, UCB and International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) as well as all the Extended MOS-AK TPC Committee, we have pleasure to invite to the 9th International MOS-AK Workshop which will be held at EECS Department, University of California, Berkeley on December, 7, 2016. Planned MOS-AK workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Important Dates:

• Preannouncement - Sept. 2016
  
• Call for Papers - Oct. 2016
  
• Final Workshop Program - Nov. 2016
  
• MOS-AK Workshop - Dec. 7 2016
•   9:00-12:00 Morning Session
• 13:00-16:00 Afternoon Session

Venue:

540 Cory Hall 
EECS Department
University of California, Berkeley
Directions to the DOP Center in Cory Hall
See also http://www.eecs.berkeley.edu/Directions/

Final MOS-AK/Berkeley Workshop Program Online 

http://www.mos-ak.org/berkeley_2016/

Online Workshop Registration:

http://www.mos-ak.org/berkeley_2016/registration.php
(any related inquiries can be sent to register@mos-ak.org)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee

WG10112016

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[mos-ak] [press note] 14th MOS-AK ESSDERC/ESSCIRC Workshop

Arbeitskreis Modellierung von Systemen und Parameterextraktion 

Modeling of Systems and Parameter Extraction Working Group

14th MOS-AK ESSDERC/ESSCIRC Workshop

Lausanne, September 12, 2016

The MOS-AK Modeling Working Group, a global compact/SPICE modeling and Verilog-A standardization forum, held its annual autumn workshop on September 12, 2016 in Lausanne (CH) as its 14th consecutive modeling event at the ESSDERC/ESSCIRC Conference. The event was coordinated by Larry Nagel, OEC (USA) and Andrei Vladimirescu, UCB (USA); ISEP (FR) representing the International MOS-AK Board of R&D Advisers. The workshop was co-sponsored by ASCENT Network (lead sponsor) and EPFL EDLab, with technical program sponsorship provided by the IEEE WiE Group (CH), Eurotraining and NEEDS of nanoHUB.org.

 

A group of the international academic researchers and modeling engineers attended 12 technical compact modeling presentations covering full development chain form the nanoscaled technologies thru semiconductor devices modeling to advanced IC design support. The MOS-AK speakers have shared their latest perspectives on compact/SPICE modeling and Verilog-A standardization in the dynamically evolving semiconductor industry and academic R&D. 

 

The workshop was opened by Prof. J. Greer; Tyndall National Institute, the MOS-AK keynote speaker, who has introduced the ASCENT Network. The ASCENT is combined resources of Tyndall (Ireland), imec (Belgium) and Leti (France) nanofabrication capabilities and electrical characterization facilities integrated into a single research infrastructure present a truly unique R&D opportunity. It provides characterization community with access to advanced test chips, flexible fabrication and advanced test and characterization equipment to accelerate development of advanced models at scales of 14nm and below.

 

The event featured additional technical presentations covering compact model development, implementation, deployment and standardization. These contributions were delivered by leading academic and industrial experts, including: Denis Rideau; STM (F), presenting a modeling study of the drain current in advanced MOSFETs. Maria-Alexandra Paun; EPFL (CH), focusing on the humidity sensors based on MWCNTs/MMA composite in SOI CMOS technological process. Mike Brinson; London Met (UK), presenting QUCS-S - maturing GPL software package for circuit simulation and compact modeling of current and emerging technology devices. Alexander Kloes; THM Giessen (D), discussing a closed-form charge-based current model of organic TFT including non-linear injection effects. Jean-Michel Sallese; EPFL (CH), discussing an advances in analytical modeling. Marco Bellini, ABB CRC (CH), presenting extraction of compact models for EMI / EMC simulations of power devices. Muhammad Nawaz; ABB CRC (S), reviewed characterization and modeling of SiC MOSFET power modules. Mansun Chan; HKUST (HK), discussing concurrent device and circuit reliability simulation. Benjamin Iñiguez; URV (SP), talking about temperature dependent GIZO TFT modeling. Mike Schwarz; THM (D), discussing analytical III-V SB MOSFET modeling and its performance analysis from room to cryogenic temperature. Matthias Bucher; TUC (GR), giving an EKV3 model update. The presentations are available online for download at http://www.mos-ak.org/lausanne_2016

 

The MOS-AK Modeling Working Group has various deliverables and initiatives including a book entitled "Open Source CAD Tools for Compact Modeling" and an open Verilog-A directory with models and supporting CAD software. The MOS-AK Association plans to continue its standardization efforts by organizing additional compact modeling meetings, workshops and courses in Europe, USA, India and China throughout 2016/2017 including:

* 9th International MOS-AK Workshop at Berkeley in the timeframe of IEDM and CMC meetings (Dec.7, 2016) 

* Spring MOS-AK Workshop in Lausanne during DATE Conference (March 31 2017)

* 2nd Sino MOS-AK Workshop in Hangzhou (June 2017)

* 15th MOS-AK ESSDERC/ESSCIRC Workshop in Leuven (Sept.11, 2017)

 

About MOS-AK Association:

MOS-AK, an international compact modeling association primarily focused in Europe, to enable international compact modeling R&D exchange in the North/Latin Americas, EMEA and Asia/Pacific Regions. The MOS-AK Modeling Working Group plays a central role in developing a common language among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact/SPICE modeling and its Verilog-A standardization and related CAD/EDA tools for the compact models development, validation/implementation and distribution.

 

About ASCENT Network:

ASCENT provides fast and easy access to the world's most advanced CMOS technologies and infrastructure including access to 14nm CMOS device data, nanoscale test chips and device characterisation facilities at Tyndall (Ireland), imec (Belgium) and Leti (France). ASCENT has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement No 654384.

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[paper] Field programmable analog array: A boon for analog world

Field programmable analog array: A boon for analog world

Dipti and B. V. R. Reddy,

2016 3rd International Conference on Computing for Sustainable Global Development 

(INDIACom), New Delhi, India, 2016, pp. 2975-2980.

Abstract: n analog chips designing, fabricating, and testing takes a lot of time, money and perfection. In contrast design of digital integrated circuits is fully automated now a day. Due to simpler nature of digital circuits, as compared to Analog circuits, leads to development of libraries and synthesis tools for fast synthesis of digital circuits. To reduce the cost and time-to-market CPLDs and FPGAs are generally used for prototyping of digital integrated circuits. But FPAAs i.e Field Programmable Analog Arrays are boon for designing of analog and mixed-signal Integrated Circuits because of rapid prototyping. FPAA is not only optimal for all solution in contrast to FPGAs but it also reduces the verification and designing cost. This again results from complex nature of analog circuits which needs factors like signal to noise ratio, bandwidth, frequency response, linearity etc. to be addressed. FPAAs are made using configurable analog blocks (CAB) and networks, which are used to provide required interconnection among Cabs. Like FPGAs, circuit functionality is much more sensitive to parasitics introduced by the programming devices in FPAA. So the design of FPAAs architecture and CABs are mutually dependent. To design an efficient FPAA, a designer needs to compromise between flexibility and the number of programmable switches in designing FPAA architectures and the CAB topologies. Various papers are studied for different topologies used in FPAAs and various applications designed with the use of FPAA. In March 2013, Paul Hasler come up with automated approach based on EKV model for characterization of device mismatch, second order defects with temperature. After verification of characterization current sources were created with 2.2% RMS error over dynamic range of 25dB. Field programmable gate array represents a new direction to analog and mixed signal domain keeping the idea of FPGAs in digital domain. RASP is useful for analog designers because they can save the analog components in the form of CABs. RASPER tool was developed for placement and routing of RASP 2.7 and RASP 2.8 versions Whereas GRASPER was developed for RASP 2.9.In digital circuits parasitic only affect the speed of operation but in analog circuits they plays a crucial role for circuit performance and functionality. Floating gate technology was used to simplify designing and implementation, increased system reliability, high precision, innovative approach. In near future FPAA technology will come up with better architecture, low power and more applications with less time to market.

keywords: Decision support systems, Handheld computers, Configurable analog block (CAB), Field programmable analog array (FPAA), Generic reconfigurable array specification and programming environment tool (GRASPER), Operational Transconductance Amplifier, Reconfigurable analog signal processor (RASP)

[read more...]

2017 1st Electron Devices Technology and Manufacturing Conference (call for #papers) https://t.co/CAj9B5ifWU

2017 1st Electron Devices Technology and Manufacturing Conference (call for #papers) https://t.co/CAj9B5ifWU

— Wladek Grabinski (@wladek60) October 27, 2016

from Twitter https://twitter.com/wladek60

October 27, 2016 at 05:08PM
via IFTTT

AMS Multi Project Wafer Service

AMS MPW Service:

ams' Multi Project Wafer (MPW) service, also known as shuttle runs, is a fast and cost-efficient prototyping service, which combines several designs from different customers onto a single wafer.

ams’ best in class MPW service offers significant cost advantages for foundry customers as the costs for wafers and masks are shared among a number of different shuttle participants. It includes the whole range of 0.18µm and 0.35µm specialty processes:

• CMOS Mixed Signal
• CMOS Mixed Signal with embedded EEPROM
• CMOS High Voltage (up to 120 Volts)
• CMOS High Voltage with embedded EEPROM
• CMOS Opto
• SiGe-BiCMOS

The complete MPW schedule including detailed start dates per process is available on the web at http://asic.ams.com/MPW

Deliverables: Participating the ams MPW service includes the delivery of 40 prototypes for design verification. Packaged engineering samples are offered within 2 days (ceramic) and 3 weeks (plastics) cycle time, respectively. The total turnaround time from MPW deadline to delivery is app. 8 weeks (CMOS). Overall, ams offers almost 150 MPW start dates in 2016 and 2017, enabled by long lasting co-operations with partner organizations such as CMP, Europractice, Fraunhofer IIS and Mosis. Customers located in APAC region may also participate via our local MPW program partners Toppan Technical Design Center Co., Ltd (TDC) and MEDs Technologies [read more...]

ARM Fellow Surveys Moore's Law at 3nm IC https://t.co/JUPsAtrkFb #papers

ARM Fellow Surveys Moore's Law at 3nm IC https://t.co/JUPsAtrkFb #papers

— Wladek Grabinski (@wladek60) October 27, 2016

from Twitter https://twitter.com/wladek60

October 27, 2016 at 10:43AM
via IFTTT

[JEDS #papers ] Characterization of RF Noise in UTBB FD-SOI MOSFET https://t.co/LNlvvNOb5V https://t.co/XQsatKslTX

[JEDS #papers ] Characterization of RF Noise in UTBB FD-SOI MOSFET https://t.co/LNlvvNOb5V https://t.co/XQsatKslTX

— Wladek Grabinski (@wladek60) October 26, 2016

from Twitter https://twitter.com/wladek60

October 26, 2016 at 05:03PM
via IFTTT

[JEDS #papers ] Characterization of RF Noise in UTBB FD-SOI MOSFET https://t.co/LNlvvNOb5V

[JEDS #papers ] Characterization of RF Noise in UTBB FD-SOI MOSFET https://t.co/LNlvvNOb5V

— Wladek Grabinski (@wladek60) October 26, 2016

from Twitter https://twitter.com/wladek60

October 26, 2016 at 04:49PM
via IFTTT

Transistor Sizing for Bias-Stress Instability Compensation in Inkjet-Printed Organic C-Inverters https://t.co/91uJURy3KA #papers

Transistor Sizing for Bias-Stress Instability Compensation in Inkjet-Printed Organic C-Inverters https://t.co/91uJURy3KA #papers

— Wladek Grabinski (@wladek60) October 25, 2016

from Twitter https://twitter.com/wladek60

October 25, 2016 at 09:07PM
via IFTTT

[ESSDERC Paper] Compact model for variability of low frequency noise due to number fluctuation effect

Compact model for variability of low frequency noise due to number fluctuation effect

N. Mavredakis and M. Bucher

2016 46th European Solid-State Device Research Conference (ESSDERC)

Lausanne, Switzerland, 2016, pp. 464-467

doi:10.1109/ESSDERC.2016.7599686

Abstract: Variability of low frequency noise (LFN) in MOSFETs is both geometry- and bias-dependent. RTS noise prevails in smaller devices where noise deviation is mostly area-dominated. As device dimensions increase, operating conditions determine noise variability maximizing it in weak inversion and increasing it with drain voltage. This dependence is shown to be directly related with fundamental carrier number fluctuation effect. A new bias- and area-dependent, physics-based, compact model for 1/f noise variability is proposed. The model exploits the log-normal behavior of LFN. The model is shown to give consistent results for average noise, variance, and standard deviation, covering bias-dependence and scaling over a large range of geometry.

Keywords: compact models, Low-frequency noise, MOSFET, Reactive power, Semiconductor device modeling, Shape, Standards, MOSFET, low frequency noise, noise variability

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7599686&isnumber=7598672

[SSE Paper] Elimination of the channel current effect on the characterization of MOSFET threshold voltage using junction capacitance measurements

Elimination of the channel current effect on the characterization of MOSFET threshold voltage using junction capacitance measurements 

Daniel Tomaszewski^a, Grzegorz Głuszko^a, Lidia Łukasiak^b,
Krzysztof Kucharski^a, Jolanta Malesinska^b

^aDivision of Silicon Microsystem and Nanostructure Technology, Instytut Technologii Elektronowej (ITE), ul. Okulickiego 5E, 05-500 Piaseczno, Poland 

^bInstitute of Microelectronics and Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662 Warsaw, Poland

Abstract: An alternative method for an extraction of the MOSFET threshold voltage has been proposed. It is based on an analysis of the MOSFET source-bulk junction capacitance behavior as a function of the gate-source voltage. The effect of the channel current on the threshold voltage extraction is fully eliminated. For the threshold voltage and junction capacitance model parameters non-iterative methods have been used. The proposed method has been demonstrated using a series of MOS transistors manufactured using a standard CMOS technology.

Keywords: MOSFET CMOS Threshold voltage Junction capacitance Parameter extraction

Cite: Tomaszewski D et al. Elimination of the channel current effect on the characterization of MOSFET threshold voltage using junction capacitance measurements. Solid State Electron (2016), http://dx.doi.org/10.1016/j.sse.2016.10.006

Sub-Minimum-Area MPW Sharing

Is Your Multi-Project Wafer Project Smaller Than the Fab Minimum Area?

Share the minimum area with other MPW customers to save mask costs

With the cost of mask sets going up with every node, even a multi-project wafer (MPW) can break your NRE budget, particularly if you plan to run multiple test spins. At 28nm, a 6mm2 area tile can cost over $100,000.

One solution is to share the minimum tile area with someone else who is using the same technology and metal stack that you are targeting. We periodically get these kinds of requests from customers. Please contact directly star@esilicon.com if you would like eSilicon to list your own MPW shuttle sharing opportunity, or if you would like eSilicon to contact you when future MPW tile sharing opportunities are available.

Following are upcoming opportunities to share a multi-project wafer (MPW) tapeout with another eSilicon customer. If you are interested, just email eSilicon.

Multi-Project Wafer Minimum Tile Sharing Opportunities for TSMC Technologies

Tapeout Month	Technology	Metal Stack	I/O	Price/mm2	Minimum Area	Final GDSII Due	Tapeout Date	Estimated Ship Date
October	65nm MS RF GP	1P9M_6x1z1u	2.5V	$4,700	1mm2	October 10	October 12	November 23
	65nm MS RF LP	1P9M_6x1z1u	2.5V	$4,700	1mm2	October 10	October 12	November 23
	180nm MS RF G	1P6M_4x1u	3.3V	$1,000	5mm2	October 24	October 26	December 7
November	40nm MS RF LP	1P10M	1.8V	$7,500	1mm2	October 31	November 2	January 17

[read more...]

#Compact #Modeling of Surface Potential, Charge, and Current in Nanoscale Transistors Under Quasi-Ballistic Regime https://t.co/BsnCEEdo8a

#Compact #Modeling of Surface Potential, Charge, and Current in Nanoscale Transistors Under Quasi-Ballistic Regime https://t.co/BsnCEEdo8a

— Wladek Grabinski (@wladek60) October 21, 2016

from Twitter https://twitter.com/wladek60

October 21, 2016 at 04:54PM
via IFTTT

Free Semiconductor Books on SemiWiki

Download free PDF versions of three pivotal semiconductor books available on SemiWiki.com:

1. Mobile Unleashed: The History of ARM
2. Fabless: The Transformation of the Semiconductor Industry
3. EDAGraffiti: 25 years of experience in EDA

Only registered SemiWiki members can access these wiki pages so if you are not already a member please join as a guest: https://www.semiwiki.com/forum/register.php

[mos-ak] [2nd Announcement and Call for Papers] 9th International MOS-AK Workshop Berkeley DEC.7, 2016

 9th International MOS-AK Workshop  

  Berkeley December 7, 2016 
    2nd Announcement and Call for Papers   

Together with the MOS-AK workshop host, Prof. Jaijeet Roychowdhury, UCB and International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) as well as all the Extended MOS-AK TPC Committee, we have pleasure to invite to the 9th International MOS-AK Workshop which will be held at EECS Department, University of California, Berkeley on December, 7, 2016. Planned MOS-AK workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors.

Important Dates:

• Preannouncement - Sept 2016
• Call for Papers - Oct. 2016
• Final Workshop Program - Nov. 2016
• MOS-AK Workshop - Dec. 7 2016

Venue:

EECS Department
University of California, Berkeley

Topics to be covered include the following among other related to the compact/SPICE modeling :

• Compact Modeling (CM) of the electron devices
• Advances in semiconductor technologies and processing
• Verilog-A language for CM standardization
• New CM techniques and extraction software
• Open Source TCAD/EDA modeling and simulation
• CM of passive, active, sensors and actuators
• Emerging Devices, TFT, CMOS and SOI-based memory cells
• Microwave, RF device modeling, high voltage device modeling
• Nanoscale CMOS devices and circuits
• Technology R&D, DFY, DFT and reliability/ageing IC Designs
• Foundry/Fabless Interface Strategies

Online MOS-AK Abstract Submission:
Prospective authors should submit online 

http://www.mos-ak.org/berkeley_2016/abstracts.php

(any related inquiries can be sent to abstracts@mos-ak.org)

Online Workshop Registration:

http://www.mos-ak.org/berkeley_2016/registration.php
(any related inquiries can be sent to register@mos-ak.org)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee

WG19102016

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Reliable Gate Stack And Substrate Parameter Extraction Based On CV Measurements For 14nm FDSOI Technology https://t.co/enF2K7D6tT #papers

Reliable Gate Stack And Substrate Parameter Extraction Based On CV Measurements For 14nm FDSOI Technology https://t.co/enF2K7D6tT #papers

— Wladek Grabinski (@wladek60) October 17, 2016

from Twitter https://twitter.com/wladek60

October 17, 2016 at 02:19PM
via IFTTT

Theoretical analysis and modeling for nanoelectronics https://t.co/PsFJzoJgC8 #papers #feedly

Theoretical analysis and modeling for nanoelectronics https://t.co/PsFJzoJgC8 #papers #feedly

— Wladek Grabinski (@wladek60) October 15, 2016

from Twitter https://twitter.com/wladek60

October 15, 2016 at 10:00PM
via IFTTT

FOSDEM 2017 EDA Devroom Call for Participation

FOSDEM 2017 Electronic Design Automation Devroom
Call for Participation

This is the call for participation in the FOSDEM 2017 devroom on Free/Open Source Software (FOSS) Electronic Design Automation (EDA) tools, to be held on Sunday 5 February 2017 in Brussels, Belgium. We are looking for contributions under the form of talks and tutorials covering the following main topics:

• Printed Circuit Board (PCB) design tools (e.g. KiCad and gEDA)
• Analogue and digital simulators (e.g. ngspice, Qucs, Gnucap, Xyce, GHDL, Icarus and Verilator)
• Any other EDA tools such as high-level tools for digital hardware design (e.g. Migen) and HDL synthesis tools (e.g.Yosys)
• Inter-project opportunities for collaboration

We hope to provide an opportunity for attendees to bring themselves up to date on the latest FOSS EDA developments, share knowledge and identify opportunities to collaborate on development tasks. Have a look at last year's event for a taste of what the EDA devroom is about.

The submission process
Please submit your proposals at 

https://penta.fosdem.org/submission/FOSDEM17 

before 1 December 2016.

If you already have a Pentabarf account (for example as a result of having submitted a proposal in the past), make sure you use it to log in and submit your proposal. Do not create a new account if you already have one. Please provide a bit of information about yourself under Person -> Description -> Abstract. When you submit your proposal (creating an "Event" in Pentabarf), make sure you choose the "Electronic Design Automation (EDA) devroom" in the track drop-down menu. Otherwise your proposal might go unnoticed. Fill in at least a title and abstract for the proposed talk and a suggested duration. Bear in mind that a lot of the value in these meetings comes from the discussions, so please be reasonable regarding the duration of the talk.

Important dates

• 1 December 2016: deadline for submission of proposals
• 11 December 2016: announcement of final schedule
• 5 February 2017: devroom day

Recordings
The FOSDEM organisers hope to be able to live-stream and record all the talks. The recordings will be published under the same licence as all FOSDEM content (CC-BY). Only presentations will be recorded, not informal discussions and whatever happens during the lunch break. By agreeing to present at FOSDEM, you automatically give permission to be recorded. The organisers will agree to make exceptions but only for exceptional and well-reasoned cases.
Mailing list

Feel free to subscribe to the mailing list of the EDA devroom to submit ideas, ask questions and generally discuss about the event.

Spread the word!
This is the third EDA devroom at FOSDEM. The first two were very well received. Let's make sure as many projects and developers as possible are present. Thanks!

[call for papers] 1st EDTM 2017

EDTM Call for Papers 

Submission deadline: November 4th, 2016

Camera ready, one page text and one page figures

1st EDTM 2017

At Toyama International Conference Center, Toyama, Japan

February 28th to March 2nd, 2017

Why EDTM has been started: System performance continues to grow, even though device scaling is saturated. Based on strong manufacturing technologies, Asia has strong potential to take an initiative for system integration. Deep-dive discussions among technical communities on materials, processes, and devices are aimed to accelerate manufacturing innovations through this forum.

1. Technical sessions

EDTM 2017 and beyond will have a strong specific technical focus, and this year’s focus being on devices and process technologies for advanced applications, IoE (Internet of Everything) and related low-power devices, advanced memories, sensors, actuators, MEMS, bio.-chips, passive devices, and all types of (exploratory) devices related to advance applications and IoE. Papers/Posters on materials and processes for enabling above-menHoned devices building in heterogeneous integration such as 2.1, 2.5 and 3D structures using wafer-level packaging process (e.g.) are of great focus. EDTM aims for highest quality, and all papers accepted would be subject to IEEE-EDS standard review processes and conference publishing guidelines. Accepted and presented papers will be published in EDTM proceedings. A selected number of high impact EDTM papers would be invited for the consideration of publication in the IEEE Journal of Electron Devices Society (J- EDS) as extended version of EDTM conference papers following the IEEE publication policy and J-EDS author-guidelines.

2. Education

• Tutorials: We will provide both the basic and advanced programs. Basic program will be presented in local language.
• Poster sessions: Primarily intended for young engineers and students. The best poster will be awarded in the conference.
• Short courses: Will bring high level programs.

3. Exhibition

Given the strong semiconductor manufacturing base in Asia, we intend to offer exhibits that will demonstrate products and technology. All of the exhibitors will have an opportunity to offer technical insight and share their knowhow. Moreover, we hope to offer Forum Making Session to engage and allow deeper discussions between device, material, and equipment engineers and technologists.

Papers in the following areas are requested by Subcommittee on:

• Devices and Manufacturing for “Cloud and Edge”
• Packaging and Manufacturing for “Cloud and Edge”
• Process, Tools, and Manufacturing
• Semiconductor Materials
• Reliability & Modeling (including compact/SPICE)

[read more...]

IEDM 2016 Session 7: Modeling and Simulation Advanced Numerical and Compact Models

IEDM 2016 Session 7

Modeling and Simulation Advanced Numerical and Compact Models

Monday, December 5, 1:30 p.m. Continental Ballroom 7-9 

Co-Chairs: Denis Rideau, STMicroelectronics 

Xing Zhou, Nanyang Technological University

1:35 PM 

7.1 A Novel Synthesis of Rent's Rule and Effective-Media Theory Predicts FEOL and BEOL Reliability of Self-Heated ICs, W. Ahn, H. Jiang, S.H. Shin and M. Alam, Purdue University

2:00 PM 

7.2 New Approach for Understanding "Random Device Physics" from Channel Percolation Perspectives: Statistical Simulations, Key Factors and Experimental Results, Z. Zhang, Z. Zhang, R. Wang, X. Jiang, S. Guo, Y. Wang, X. Wang*, B. Cheng*, A. Asenov* and R. Huang, Peking University, *Synopsys

2:25 PM 

7.3 Oxide-Based Analog Synapse: Physical Modeling, Experimental Characterization, and Optimization, B. Gao, H. Wu, J. Kang*, H, Yu**, H. Qian, Tsinghua University, *Peking University, **Southern University of Science and Technology

2:50 PM 

7.4 Extending the Bounds of Performance in E-mode p-channel GaN MOSHFETs, A. Kumar and M. De Souza, The University of Sheffield

3:15 PM 

7.5 NSP: Physical Compact Model for Stacked-planar and Vertical Gate-All-Around MOSFETs, O. Rozeau, S. Martinie, T. Poiroux, F. Triozon, S. Barraud, J. Lacord, Y.-M. Niquet*, C. Tabone, R. Coquand, E. Augendre, M. Vinet, O. Faynot, and J.-C. Barb, CEA-Leti, *CEA-INAC

3:40 PM 

7.6 A Physics-Based Compact Model for Material- and Operation-Oriented Switching Behaviors of CBRAM, Y. Zhao, J. Hu, P. Huang, F. Yuan*, Y. Chai*, X. Liu and J. Kang, Peking University, *The Hong Kong Polytechnic University

4:05 PM 

7.7 Multi-Domain Compact Modeling for GeSbTe-based Memory and Selector Devices and Simulation for Large-scale 3-D Cross-Point Memory Arrays, N. Xu, J. Wang, Y. Deng, Y. Lu, B. Fu, W. Choi, U. Monga*, J. Jeon*, J. Kim*, K.-H. Lee* and E. S. Jung*, Samsung Semiconductor Inc., *Samsung Electronics

[read more...]

Compound Semiconductor Technical Committee Meeting

SEMI® International Standards Program

Compound Semiconductor Technical Committee Meeting

Fraunhofer IISB, Schottkystrasse 10, D-91058 Erlangen, Germany

Thu 13th October 2016 14:00 to 16:30

Co-chairs:
• Dr. Arnd-Dietrich Weber, SiCrystal
• N.N. 

Agenda: European Compound Semiconductor Committee Meeting

Task Force meetings – tbd

14:00 Welcome and Self-Introductions all

14:05 SEMI Standards Overview and Legal Reminders SEMI Staff

14:10 Review of the minutes and action items from the previous meeting SEMI Staff

14:15 Task Force Reports (~5 minutes each)

SiC-Task Force A. Weber

Status M55 5-year review (doc 4689)

Status M81 5-year-review (doc 6015)

Contactless Capacitive Resistivity Task Force W. Jantz

14:30 Discussion and approval of doc 4689 (M55 review) for ballot A. Weber

15:00 5-Year-Review of published documents

5-year-review of M54 (Guide for semi-insulating GaAs parameters): discuss and

approve TFOF and SNARF U. Kretzer

dentification and discussion of action items all

15:30 Compound Materials Liaison Reports

North America

Japan SEMI Staff

15:45 Any Other Business / Questions A. Weber

16:00 Next Meetings

16:15 Adjourn 

Lectures on Electromagnetism https://t.co/nxi9p90Cte #papers

Lectures on Electromagnetism https://t.co/nxi9p90Cte #papers

— Wladek Grabinski (@wladek60) October 12, 2016

from Twitter https://twitter.com/wladek60

October 12, 2016 at 10:55AM
via IFTTT

[website] Open Circuit Design Software

Visit the Open Circuit Design Software to learn more about the major electronic design automation (EDA) tools hosted by Open Circuit Design:

• Magic, the VLSI layout editor, extraction, and DRC tool
• XCircuit, the circuit drawing and schematic capture tool
• IRSIM, the switch-level digital circuit simulator
• Netgen, the circuit netlist comparison (LVS) and netlist conversion tool
• Qrouter, the over-the-cell (sea-of-gates) detail router
• Qflow, a complete digital synthesis design flow using open-source software and open-source standard cell libraries
• PCB, the printed circuit board layout editor

[More about Open Circuit Design Software]

[paper] Well-Posed Models of Memristive Devices

Well-Posed Models of Memristive Devices

Tianshi Wang, Jaijeet Roychowdhury

(Submitted on 15 May 2016)

Existing compact models for memristive devices (including RRAM and CBRAM) all suffer from issues related to mathematical ill-posedness and/or improper implementation. This limits their value for simulation and design and in some cases, results in qualitatively unphysical predictions. We identify the causes of ill-posedness in these models. We then show how memristive devices in general can be modelled using only continuous/smooth primitives in such a way that they always respect physical bounds for filament length and also feature well-defined and correct DC behaviour. We show how to express these models properly in languages like Verilog-A and ModSpec (MATLAB). We apply these methods to correct previously published RRAM and memristor models and make them well posed. The result is a collection of memristor models that may be dubbed "simulation-ready", i.e., that feature the right physical characteristics and are suitable for robust and consistent simulation in DC, AC, transient, etc., analyses. We provide implementations of these models in both ModSpec/MATLAB and Verilog-A.

Subjects: Emerging Technologies (cs.ET); Computational Engineering, Finance, and Science (cs.CE)
Cite as: arXiv:1605.04897 [cs.ET]
(or arXiv:1605.04897v1 [cs.ET] for this version)