Showing posts with label
paper
.
Show all posts
Showing posts with label
paper
.
Show all posts
Jan 15, 2020
EKV2.6 conference paper reached 50 reads
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W. Grabinski et al., "FOSS EKV2.6 Verilog-A Compact MOSFET Model," ESSDERC, Krakow, Poland, 2019, pp. 190-193. doi: 10....
Oct 10, 2019
article with 700 reads
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Wladek Grabinski, Matt Bucher,Jean-Michel Sallese and François Krummenacher Advanced Compact Modeling of the Deep Submicron Technologies...
Sep 3, 2019
Article reached 1,000 reads
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A. Bazigos, M. Bucher, J. Assenmacher, S. Decker, W. Grabinski and Y. Papananos An Adjusted Constant-Current Method to Determine Satura...
Jun 6, 2019
[paper] Novel General Compact Model Approach
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A Novel General Compact Model Approach for 7nm Technology Node Circuit Optimization from Device Perspective and Beyond Qiang Huo, Zhenh...
Jun 22, 2017
[paper] Design Strategies for Ultralow Power 10nm FinFETs
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Design Strategies for Ultralow Power 10nm FinFETs Abhijeet Walkea a , Garrett Schlenvogtb b , Santosh Kurineca a a Department of Elect...
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