[paper] Novel General Compact Model Approach

A Novel General Compact Model Approach for 7nm Technology Node Circuit Optimization from Device Perspective and Beyond

Qiang Huo, Zhenhua Wu, Weixing Huang, Xingsheng Wang, Senior Member, IEEE, Geyu Tang, Jiaxin Yao, Yongpan Liu, Feng Zhang, Ling Li, and Ming Liu, Fellow,IEEE

Abstract: This work presents a novel general compact model for 7nm technology node devices like FinFETs. As an extension of previous conventional compact model that based on some less accurate elements including one-dimensional Poisson equation for three-dimensional devices and analytical equations for short channel effects, quantum effects and other physical effects, the general compact model combining few TCAD calibrated compact models with statistical methods can eliminate the tedious physical derivations. The general compact model has the advantages of efficient extraction, high accuracy, strong scaling capability and excellent transfer capability. As a demo application, two key design knobs of FinFET and their multiple impacts on RC control ESD power clamp circuit are systematically evaluated with implementation of the newly proposed general compact model, accounting for device design, circuit performance optimization and variation control. The performance of ESD power clamp can be improved extremely. This framework is also suitable for pathfinding researches on 5nm node gate-all-around devices, like nanowire (NW) FETs, nanosheet (NSH) FETs and beyond.

Index Terms: General compact model, FinFET, ESD power clamp, 7 nm technology node and beyond.

Fig. (A) The schematic of partial parameters of FinFET. (B) Key design rules of 7nm node FinFET as according to [1]. 

Access: https://arxiv.org/ftp/arxiv/papers/1905/1905.11207.pdf

REF: [1] S. Narasimha et al.“A 7nm CMOS technology platform for mobile and high performance compute application,” IEEE International Electron Devices Meeting (IEDM), Dec. 2017, pp. 29.5.1-29.5.4, doi: 10.1109/IEDM.2017.8268476.