Revolution EDA has two updates to share this month:
- a browser-based cloud trial environment is now live, and
- hierarchical Layout vs Schematic (LVS) verification has been added to the platform
Cloud Trial Environment
Revolution EDA can now be evaluated directly in a web browser, eliminating the need for local installation. The trial is available at cloud.reveda.eu:3000. To start a session, enter your email address and click the login link you receive. Each session runs for one hour.
The trial environment includes schematic capture, simulation workflows, layout editing and verification, and an integrated AI terminal. Email addresses are not stored unless you opt in to receive updates. Revolution EDA is the first European cloud-based EDA platform focused on analogue and mixed-signal IC design.
Hierarchical LVS Verification
Revolution EDA now includes hierarchical Layout vs Schematic (LVS) verification. LVS confirms that a chip's physical layout matches its schematic, catching errors before fabrication. The initial implementation covers the IHP SG13G2 technology node, using IHP rule decks run through KLayout in headless mode.
The tool runs directly from within the layout editor. It automatically extracts netlists, verifies device and pin connections across hierarchy levels, and produces detailed violation reports. After reviewing violations, corrections can be applied and the design re-verified without leaving the application. Future additions include RC extraction, cross-probe navigation, additional PDK support, and AI-assisted debugging. Like all Revolution EDA tools, LVS is available under the Mozilla Public License v2.0 with Commons Clause — no licensing fees or subscription requirements.
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