1st Semiconductor Design Workshop in Yamagata

Ministry of Economy, Trade and Industry

Tohoku Bureau of Economy, Trade and Industry

1st Semiconductor Design Workshop in Yamagata

Date: December 20, 2024 (Friday)

Time: 1:00pm-5:00pm

Why not experience semiconductor design hands-on with the instructor on your own PC? This is a valuable opportunity to learn the basics of semiconductor design with intimate and detailed guidance in a small class setting.

[paper] Roadmap for Schottky Barrier Transistors

Eva Bestelink1*, Giulio Galderisi2, Patryk Golec1, Yi Han3, Benjamin Iniguez4, Alexander Kloes5, Joachim Knoch6, Hiroyuki Matsui7, Thomas Mikolajick2,8, Kham M. Niang9, Benjamin Richstein6, Mike Schwarz5, Masiar Sistani10, Radu A. Sporea1, Jens Trommer2, Walter M. Weber10,
Qing-Tai Zhao3 and Laurie E. Calvet11

Roadmap for Schottky Barrier Transistors

IOP Nano Futures in press (2024)

DOI: 10.1088/2399-1984/ad92d1

1 Advanced Technology Institute, University of Surrey, Guildford, UK
2 Namlab gGmbH, Nöthnitzer Str. 64a, 01187 Dresden, Germany
3 Peter Grünberg Institute, Forschungszentrum Jülich, 52428 Jülich, Germany
4 DEEEA, Universitat Rovira I Virgili, Tarragona, Spain,
5 NanoP, THM University of Applied Sciences, 35390 Giessen, Germany,
6 Institute of Semiconductor Electronics, RWTH Aachen University, Germany
7 Research Center for Organic Electronics (ROEL), Yamagata University, Japan
8 Chair for Nanoelectronics, TU Dresden, Germany
9 Electrical Engineering, Cambridge University, UK
10 Institute of Solid State Electronics, TU Wien, Vienna, Austria
11 LPICM, CNRS-Ecole Polytechnique, IPP, 91120 Palaiseau, France

Abstract: In this roadmap we consider the status and challenges of technologies that use the properties of a rectifying metal-semiconductor interface, known as a Schottky barrier, as an asset for device functionality. We discuss source gated transistors, which allow for excellent electronic characteristics for low power, low frequency environmentally friendly circuits. Also considered are reconfigurable field effect transistors, where the presence of two or more independent gate electrodes can be used to program different functionalities at the device level, providing an important option for ultrasecure embedded devices. Both types of transistors can be used for neuromorphic systems, notably by combining them with ferroelectric Schottky barrier transistors, which enable a large number of analog states. At cryogenic temperatures, SB transistors can advantageously serve for the control electronics in quantum computing devices. If the source/drain of the metallic contact becomes superconducting, Josephson junctions with a tunable phase can be realized for scalable quantum computing applications. Developing applications using Schottky barrier devices requires physicsbased and compact models that can be used for circuit simulations, which are also discussed. The roadmap reveals that the main challenges for these technologies are improving processing, access to industrial technologies and modeling tools for circuit simulations.

Fig: Illustration of the different applications of the SB Devices

Aknowleegements: RAS and EB acknowledge support from the Engineering and Physical Sciences Research Council (EPSRC) under Grants EP/V002759/1, EP/R028559/1, and EP/R511791/1, and from the Royal Society of Great Britain under Grants IES\R2\202056, IES\R3\193072, IEC\R3\183042, and IES\R3\170059. JT and GG are supported from the European Union’s Horizon Europe research and innovation programme under grant agreement No 101135316, SENSOTERIC. LEC and BI are supported from the European Union’s Horizon Europe research and innovation program under grant agreement No 101099555, BAYFLEX. Q-T Zhao, Y. Han, B. Richstein and J. Knoch gratefully acknowledge support from Deutsche Forschungsgemeinschaft under grant nos. KN 545/28, KN 545/29, and ZH-639/3. Q-T Zhao acknowledges partially support by the German BMBF project “NeuroTEC” (16ME0398K). KMN acknowledges support from the Engineering and Physical Sciences Research Council (EPSRC) under Grants EP/M013650/1 and EP/W009757/1. LEC acknowledges funding from the ANR under contract ANR-21-FAI1-0006-01.

[paper] Bendable non-silicon RISC-V microprocessor

Emre Ozer, Jedrzej Kufel, Shvetank Prakash2, Alireza Raisiardali, Olof Kindgren3, Ronald Wong,
Nelson Ng, Damien Jausseran, Feras Alkhalil, David Kong2, Gage Hills2, Richard Price
and Vijay Janapa Reddi2

Bendable non-silicon RISC-V microprocessor

Nature, vol. 634, pp. 341–346 (2024) 

DOI: 10.1038/s41586-024-07976-y

1 Pragmatic Semiconductor, Cambridge, UK
2 Harvard University, Cambridge, MA, USA

3 Qamcom, Karlstad, Sweden

Abstract: Semiconductors have already had a very profound effect on society, accelerating scientific research and driving greater connectivity. Future semiconductor hardware will open up new possibilities in quantum computing, artificial intelligence and edge computing, for applications such as cybersecurity and personalized healthcare. By nature of its ethos, open hardware provides opportunities for even greater collaboration and innovations across education, academic research and industry. Here we present Flex-RV, a 32-bit microprocessor based on an open RISC-V instruction set fabricated with indium gallium zinc oxide thin-film transistors on a flexible polyimide substrate, enabling an ultralow-cost bendable microprocessor. Flex-RV also integrates a programmable machine learning (ML) hardware accelerator inside the microprocessor and demonstrates new instructions to extend the RISC-V instruction set to run ML workloads. It is implemented, fabricated and demonstrated to operate at 60kHz consuming less than 6mW power. Its functionality when assembled onto a flexible printed circuit board is validated while executing programs under flat and tight bending conditions, achieving no worse than 4.3% performance variation on average. Flex-RV pioneers an era of sub-dollar open standard non-silicon 32-bit microprocessors and will democratize access to computing and unlock emerging applications in wearables, healthcare devices and smart packaging.

FIG a. Layout of the 9×6 mm2 test chip containing two Flex-RV microprocessors

b. The FlexPCB on which the die is assembled.

Data availability
Source data are provided with this paper.

Code availability

Serv is an open-source CPU, which is freely available at GitHub (https://github.com/olofk/serv). The source code of the test benchmarks, the changes made in the Serv CPU Verilog code, and the Verilog code of the ML hardware accelerator are available from the corresponding author upon request.

[WOSET] Q&A at OpenPDK session

Indira Iyer Almeida, Sumanto Kar, Wladek Grabinski joined a great Q&A at #OpenPDK session at #WOSET

Workshop on Open-Source EDA Technology (WOSET) was organized by Prof. Matthew Guthaus and his R&D Team. WOSET 2024 Schedule is available online

 

 

[paper] TCAD for Circuits and Systems

Z. Stanojevic, X. Klemenschits, G. Rzepa, F. Mitterbauer, C. Schleich,

F. Schanovsky, O. Baumgartner, and M. Karner

TCAD for Circuits and Systems: Process Emulation, Parasitics Extraction, Self-Heating

2024 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium

BCICTS, Fort Lauderdale, FL, USA, 2024, pp. 294-297

doi: 10.1109/BCICTS59662.2024.10745677

1 Global TCAD Solutions GmbH., Boesendorferstraße 1/12, 1010 Vienna, Austria

Abstract: We present TCAD-based methodologies that go beyond process and device simulations of single transistors. We show that TCAD solvers can be used as effective tools to resolve the intricacies of current and future technology nodes that are otherwise difficult to access using EDA-level methods alone.

Fig: Single NMOS/PMOS FinFET with the local contacts and their parasitic R/C-components; fitting results for NMOS and PMOS FinFET: gate capacitance, transfer characteristics, output characteristics

[paper] Open-source Cell Libraries

Chenlin Shi1, Shinobu Miwa1, Tongxin Yang1, Ryota Shioya2, Hayato Yamaki1
and Hiroki Honda1
"CNFET-OCL: Open-source Cell Libraries for Advanced CNFET Technologies"

IEEE Access (2024)

DOI: 10.1109/ACCESS.2024.0429000

1 Department of Computer and Network Engineering, The University of Electro-Communications, Chofu, Tokyo (J)

2 Department of Creative Informatics, Graduate School of Information Science and Technology, Uni Tokyo, Bunkyo (J)

Abstract: In this paper, we propose CNFET-OCL, the first open-source cell libraries for 5-nm and 7nm carbon nanotube field-effect transistor (CNFET) technologies. Our CNFET-OCL is designed to emulate the predictive 5-nm and 7-nm CNFET technologies presented in a published paper. We achieved this by performing a number of SPICE simulations based on an open-source CNFET SPICE model and making certain assumptions used in previous work. Each of our cell libraries includes two types of delay model (i.e., the composite current source and nonlinear delay model), each having 56 typical standard cells, which is sufficient to design various VLSI circuits. CNFET-OCL fully supports both logic synthesis and timing-driven place and route design in the Cadence design flow. Our experimental results demonstrate that CNFET-OCL can achieve performance levels comparable to those reported in previous studies on CNFETs. Consequently, CNFET-OCL can serve as an effective evaluation tool for the CNFET research community.

FIG: I–V characteristics of transistors used in CNFET5, CNFET7 and ASAP7
with cross-section of a CNFET device.

Acknowledgments: This work is partially supported by JSPS KAKENHI under grant number 18K19778 and 23K18461, and VLSI Design and Education Center (VDEC), The University of Tokyo with the collaboration with CADENCE Corporation and Synopsys Corporation. We thank Logic Research Co., Ltd. for helping generate the LIBERTY files and Edanz (https://jp.edanz.com/ac) for editing a draft of this manuscript. We also thank Mr. Dooseok Yoon for his invaluable help with the SPICE netlist simulation of PROBE3.0.

[anysilicon.com] Open Source CAD/EDA Tools

A List of Open Source EDA Tools

<https://anysilicon.com/the-ultimate-guide-to-open-source-eda-tools/>

The FOSS CAD/EDA tools outlined adhere to establish an open source design flow, essential for IC development. The process involves several steps: describing IC schematics, analog/RF circuits, digital circuit in HDL format, followed by synthesis, placement and routing, and culminating with post-layout simulations.

CppSim: has been actively used since 2002. It is used for commercial and academic purposes. It performs system-level simulations of mixed-signal circuits. It automatically produces, compiles, and executes C++ code per the schematic design you produce.

Electric: among one the powerful CAD systems which can handle different types of circuit design tasks including MOS, Bipolar, schematics, printed circuitry, hardware description languages, etc. It can analyze design rule checking, simulation, and network comparison. It can perform synthesis as well, like routing, compaction, silicon compilation, PLA generation, and compensation.

eSim: an integrated tool built from open source software such as KiCad, Ngspice, Verilator, Makerchip, GHDL, and OpenModelica. It is an EDA tool for circuit design, simulation, and analysis.

IRSIM: a tool for simulating digital circuits. It is a switch-level simulator, where transistors are treated as ideal switches. In this simulator, the circuit under simulation can be modified and then incrementally restimulated. It maintains the history of circuit activity and only restimulates the part of the circuit that deviates from its history.

Mosaic: Analogue integrated circuit designs can be created and simulated using the tool mosaic. It emphasizes a cutting-edge, user-friendly interface, immediate design feedback, design reuse, verification, and automation. Regardless of your internet connection, Mosaic will remain quick and accessible and synchronize your modifications when you reconnect.

Ngspice: An open-source mixed-signal SPICE simulator. ngspice has a command line input interface and plots the waveforms. This tool offers active development and improved stability. ngspice is based on three open-source free-software packages: Spice3f5, Xspice, and Cider1b1:

QUCS(Quite Universal Circuit Simulator): a well-advanced circuit simulator that supports all kinds of simulations like DC, AC, s-parameter, noise, transient analysis, etc. It allows importing existing SPICE models as well.

X Circuit: The schematic diagrams drawn from the schematic capture program do not produce an image that is suitable for publication. Engineers have to draw the schematic with the help of general-purpose drawing tools. It is a drawing tool that is specifically for circuits only. It can produce high-quality schematic diagrams and other figures that are suitable for publication purposes.

Xschem: a schematic capture program for VLSI and ASIC design.

XYCE: a SPICE-compatible software, written in C++ and using MPI (Message Passing Implementation). It also includes Trilinos ( Sandra’s open source library), which includes KLU direct solver and many more circuit-specific solvers.

ChipVault: an organization tool for HDL. It allows for hierarchical file navigation, sorting, and editing.

EDA Playground: a free web application for HDL (including Verilog, system Verilog, VHDL, and other HDLs) simulations and synthesis. It generates a browser-based waveform viewer after a successful simulation. It is easy to use because no download is required and code sharing is easy.

GHDL: translates VHDL files directly into machine code and hence faster compilation and analysis of code than any other interpreted simulator.

Icarus Verilog: a compiler for Verilog HDL as described in the IEEE-1364 standard. With the help of written Verilog code, it compiles the code into some target format. This tool supports a waveform viewer named GTKWave.

Migen: a python-based tool that applies advanced software concepts like OOPs, and metaprogramming in the VLSI design process and building complex digital hardware. It is a brand new programming language based on FHDL

Yosys: a synthesis tool that can handle Verilog code and can synthesize complex projects as well.

Fairly Good Router: a software for routing, based on Lagrange multipliers. It is an academic tool and it is based on similar routers used on industrial levels.

KLayout: KLayout is an editor that helps with the layout. It is also helpful in changing and creating GDS and OASIS files.

Magic: is considered one of the easiest tools for circuit layout. This tool supports LVS and DRC as well.

QRouter: a tool for routing based on the standard Lee maze routing algorithm. It supports LEF and DEF formats as input and output.

OpenSTA: is used to verify the timings of a circuit at the gate level.

OpenTimer: A high-performance, commercial-grade timing analysis tool. It helps IC designers with its interactive analysis to verify circuit timings. It supports both path-based and graph-based timing analysis. It is relatively a new tool that supports industry-standard format support like  .lib, .v, .spef, and .sdc.

HiTas: Another tool for static timing analysis.

Netgen: is a verification tool for comparing a layout to a netlist. To ensure this physical verification and LVS is carried out.  Netgen version 1.5 is considered a commercial-grade tool.

Dragon: is an effective tool for standard cell placement for variable and fixed die ASIC design.

Gdsfactory: Since gdsfactory is entirely written in Python, some Python concepts are necessary. It is built on top of KLayout, gdspy (Python library for producing GDSII files), and Phidl (Python module for GDS layout and cad geometry).

Alliance/Coriolis VLSI CAD Tools: Alliance / Coriolis is a free software toolchain for VLSI design. The input is HDL (Verilog or VHDL) and the output is GDSII, which is all set for ASIC manufacture.

Qflow: Provides a set of tools and methods to turn an HDL code (written in Verilog or VHDL) into a physical circuit. It is capable of handling sub-systems like host-to-device communication, signal processing, arithmetic logic unit, etc.

OpenLane:  An automated VLSI design flow for digital synthesis. It is a collection of open-source tools. It performs all the tasks from RTL to GDS-II with the help of a predefined set of commands for design explanation and optimization. It has two modes.

OpenROAD: is a flow of open source tools for ASIC design. The whole flow is automated for digital SoC layout generation, focusing on the RTL-to-GDSII phase of system-on-chip design.

Silicon Compiler: automatically translates source code to hardware design. There are three steps.

IBTIDA:Fully open-source ASIC implementation of Chisel-generated System on a Chip

Recent Compact Modeling Papers

[1] Hao Su, Yunfeng Xie, Yuhuan Lin, Haihan Wu, Wenxin Li, Zhizhao Ma, Yiyuan Cai, Xu Si, Shenghua Zhou Guangchong Hu, Yu He Feichi Zhou, Xiaoguang Liu, Longyang Lin, Yida Li, Hongyu Yu, and Kai Chen; "Characterizations and Framework Modeling of Bulk MOSFET Threshold Voltage Based on a Physical Charge-Based Model Down to 4 K." In 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), pp. 733-736. IEEE, 2024. doi: 10.1109/ESSERC62670.2024.10719583

[2] Tung, Chien-Ting, Sayeef Salahuddin, and Chenming Hu; "A SPICE-Compatible Neural Network Compact Model for Efficient IC Simulations." In 2024 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 01-04. IEEE, 2024.

[3] Jana, Koustav, Shuhan Liu, Kasidit Toprasertpong, Qi Jiang, Sumaiya Wahid, Jimin Kang, Jian Chen, Eric Pop, and H-S. Philip Wong; "Modeling and Understanding Threshold Voltage and Subthreshold Swing in Ultrathin Channel Oxide Semiconductor Transistors." In 2024 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 01-04. IEEE, 2024.

[4] Manganaro, Gabriele. "Rethinking mixed-signal IC design." In 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), pp. 552-556. IEEE, 2024

[5] Wager, John F., Jung Bae Kim, Daniel Severin, Zero Hung, Dong Kil Yim, Soo Young Choi, and Marcus Bender; "Dual-Layer Thin-Film Transistor Analysis and Design." IEEE Open Journal on Immersive Displays (2024).