[paper] Characteristics and ultra-high total ionizing dose response

Termo, Gennaro, Giulio Borghello, Federico Faccio, Kostas Kloukinas, Michele Caselle, Alexander Friedrich Elsenhans, Ahmet Cagri Ulusoy, Adil Koukab, and Jean-Michel Sallese

 Characteristics and ultra-high total ionizing dose response 

of 22 nm fully depleted silicon-on-insulator

Journal of Instrumentation 19, no. 03 (2024): C03039

DOI 10.1088/1748-0221/19/03/C03039

a CERN, Geneva, Switzerland

b École Polytechnique Fédérale de Lausanne, Switzerland

c Karlsruhe Institute of Technology, Germany

Abstract: The radiation response of MOS transistors in a 22 nm Fully Depleted Silicon-On-Insulator (FDSOI) technology exposed to ultra-high total ionizing dose (TID) was investigated. Custom structures including n- and p-channel devices with different sizes and threshold voltage flavours were irradiated with X-rays up to a TID of 100 Mrad(SiO2) with different back-gate bias configurations, from −8 V to 2 V. The investigation revealed that the performance is significantly affected by TID, with the radiation response being dominated by the charge trapped in the buried oxide.

Fig: Schematic of the irradiated transistors in 22 nm FDSOI 

Complementary paper:

[1] Termo, Gennaro, Giulio Borghello, Federico Faccio, Stefano Michelis, A. Koukab, and J-M. Sallese. "Fab-to-fab and run-to-run variability in 130 nm and 65 nm CMOS technologies exposed to ultra-high TID." Journal of Instrumentation 18, no. 01 (2023): C01061.

[paper] Chip Placement with Deep Learning

Azalia Mirhoseini, Anna Goldie, Mustafa Yazgan, Joe Jiang, Ebrahim Songhori, Shen Wang, Young-Joon Lee, Eric Johnson, Omkar Pathak, Sungmin Bae Azade, Nazi Jiwoo, Pak Andy, Tong Kavya Srinivasa, William Hang, Emre Tuncer, Anand Babu Quoc, Le James Laudon, Richard Ho, Roger Carpenter, Jeff Dean

Chip placement with deep reinforcement learning

arXiv preprint:2004.10746 (2020)

Abstract: In this work, we present a learning-based approach to chip placement, one of the most complex and time-consuming stages of the chip design process. Unlike prior methods, our approach has the ability to learn from past experience and improve over time. In particular, as we train over a greater number of chip blocks, our method becomes better at rapidly generating optimized placements for previously unseen chip blocks. To achieve these results, we pose placement as a Reinforcement Learning (RL) problem and train an agent to place the nodes of a chip netlist onto a chip canvas. To enable our RL policy to generalize to unseen blocks, we ground representation learning in the supervised task of predicting placement quality. By designing a neural architecture that can accurately predict reward across a wide variety of netlists and their placements, we are able to generate rich feature embeddings of the input netlists. We then use this architecture as the encoder of our policy and value networks to enable transfer learning. Our objective is to minimize PPA (power, performance, and area), and we show that, in under 6 hours, our method can generate placements that are superhuman or comparable on modern accelerator netlists, whereas existing baselines require human experts in the loop and take several weeks.

Fig: Visualization of placements. On the left, zero-shot placements from the pre-trained policy and on the right, placements from the finetuned policy are shown. The zero-shot policy placements are generated at inference time on a previously unseen chip. The pre-trained policy network (with no fine-tuning) places the standard cells in the center of the canvas surrounded by macros, which is already quite close to the optimal arrangement and in line with the intuitions of physical design experts.

Acknowledgments: This project was a collaboration between Google Research and the Google Chip Implementation and Infrastructure (CI2) Team. We would like to thank Cliff Young, Ed Chi, Chip Stratakos, Sudip Roy, Amir Yazdanbakhsh, Nathan Myung-Chul Kim, Sachin Agarwal, Bin Li, Martin Abadi, Amir Salek, Samy Bengio, and David Patterson for their help and support.

[book] NANOELEKTRONIK Bauelemente der Zukunft

 

NANOELEKTRONIK

Bauelemente der Zukunft

Edition: 2., updated and expanded edition

• Alexander Klös

eISBN: 978-3-446-47900-5

Print ISBN: 978-3-446-47899-2

© 2024 Carl Hanser Verlag GmbH & Co. KG

Vorwort zur 2. Auflage

Kaum ein Gebiet der Ingenieurwissenschaften entwickelt sich so rasant wie die Nanoelektronik. Seit der Drucklegung der ersten Auflage dieses Buchs wurden neue Bauelementkonzepte entwickelt, die für die weitere Entwicklung der Großintegration sehr vielverspechend sind.

Heute bereiten die drei wirtschaftlich größten Halbleiterhersteller den Übergang zu sogenannten Nanosheet-Transistoren vor. Durch konsequente Weiterentwicklung dieses Konzepts haben 2D-Materialien in der Nanoelektronik inzwischen eine große Bedeutung erlangt und werden für neue Transistorstrukturen erforscht. Diese Entwicklungen sind jetzt in der neuen Auflage des Buchs enthalten.

Weiterhin wurden die Grundlagenkapitel zur Halbleiterphysik erweitert, um dem Anspruch des Buchs als umfassendes und alleiniges Begleitbuch für Vorlesungen auch in Masterstudiengängen gerecht zu werden. Hierbei wird insbesondere der Einführung der Bandstruktur von Halbleitern und der Berechnung von Tunnelströmen mehr Raum gewidmet. Eine Vielzahl von kleineren Änderungen und Aktualisierungen in allen sonstigen Kapiteln und eine Übersicht der empfohlenen Simulationstools auf der Plattform nanohub.org runden die neue Auflage ab.

An dieser Stelle sei darauf hingewiesen, dass aus Gründen einer einheitlichen Darstellung im Text und in den grafischen Darstellungen der Punkt als Dezimaltrennzeichen entsprechend dem englischen Sprachraum verwendet wird.

Chapter	Pages
Nanoelektronik	1–13
1 Einführung in die Nanoelektronik	15–18
2 Eigenschaften von Halbleitern	19–38
3 Teilchen und Wellen	39–64
4 Bandstruktur und Bändermodell	65–104
5 Ladungstransport in Halbleitern	105–124
6 Grundlagen der Halbleitertechnologie	125–146
7 Klassische Bauelemente der Mikroelektronik	147–222
8 Digitale CMOS-Schaltungstechnik	223–242
9 Nanostruktur-Feldeffekttransistoren	243–302
10 Alternative Nanostruktur-MOSFETs	303–334
Konstanten und Materialparameter	335–336
Simulationstools	337–344
Formelzeichen	345–350
Literatur	351–354
Index	355–362

[OSDA 2024] 4th Workshop on Open-Source Design Automation

4th Workshop on Open-Source Design Automation

OSDA 2024

at DATE Palacio De Congresos València, Spain

25 Mar 2024

Organiser: Christian Krieg, TU Wien, Austria

OSDA intends to provide an avenue for industry, academics, and hobbyists to collaborate, network, and share their latest visions and open-source contributions, with a view to promoting reproducibility and re-usability in the design automation space. DATE provides the ideal venue to reach this audience since it is the flagship European conference in this field -- particularly poignant due to the recent efforts across the European Union (and beyond) that mandate “open access” for publicly funded research to both published manuscripts as well as software code necessary for reproducing its conclusions. A secondary objective of this workshop is to provide a peer-reviewed forum for researchers to publish “enabling” technology such as infrastructure or tooling as open-source contributions -- standalone technology that would not normally be regarded as novel by traditional conferences -- such that others inside and outside of academia may build upon it.

Agenda:

Christian Krieg; Post-Doctoral Researcher and Teacher at TU Wien

Welcome Session

Luca Carloni ;Professor at Columbia University

ESP: An Open-Source Platform for Collaborative Design of Heterogeneous Systems-on-Chip

Jean-Paul Chaput; Engineer at Sorbonne Université

Update on the Coriolis EDA Toolchain

Dirk Koch; Professor at Heidelberg University

FABulous: An embedded eFPGA Framework - an Update

Matthew Venn; Founder at YosysHQ, TinyTapeout

Demo Pitch: Tiny Tapeout

Claire Xenia Wolf; CTO at YosysHQ

Yosys

Frans Skarman PhD Student at Linköping University

Surfer -- An Extensible and Snappy Waveform Viewer

Poster Session

• Vojtech Mrazek
  An Open-Source Automated Design Space Exploration Framework for Approximate Accelerators in FPGAs and ASICs
• Marc Solé i Bonet, Aridane Alvarez Suarez and Leonidas Kosmidis
  The METASAT Hardware Platform v1.1: Identifying the Challenges for its RISC-V CPU and GPU Update
• Louis Ledoux and Marc Casas
  The Grafted Superset Approach: Bridging Python to Silicon with Asynchronous Compilation and Beyond
• Manfred Schlägl, Christoph Hazott and Daniel Große
  RISC-V VP++: Next Generation Open-Source Virtual Prototype
• Guillem López-Paradís, Brian Li, Adrià Armejach, Stefan Wallentowitz, Miquel Moretó and Jonathan Balkind
  Using Supercomputers to Parallelize RTL Simulations
• Davide Cieri
  Hog (HDL on git): a tool to manage HDL code on a git repository
• Jakob Ratschenberger and Harald Pretl
  RALF: A Reinforcement Learning Assisted Automated Analog Layout Design Flow
• Ajeetha Kumari Venkatesan, Anirudh Pradyumnan Srinivasan, Deepa Palaniappan
  Adding configurability to PySlint using TOML
• Lucas Klemmer and Daniel Grosse
  WSVA: A SystemVerilog Assertion to WAL Compiler

[FOSSEE] Better Education

FOSSEE (Free/Libre and Open Source Software for Education) project promotes the use of free open source software (FOSS) tools in academia and research. The FOSSEE project is part of the National Mission on Education through Information and Communication Technology (ICT), Ministry of Education (MoE), Government of India. 

Below is the list of projects which are promoted by FOSSEE.

• Scilab 
  free/libre and open source software for numerical computation developed by Scilab Enterprises, France. Scilab also includes Xcos which is an open source alternative to Simulink.
• Python 
  general-purpose, high-level, remarkably powerful dynamic programming language that is used in a wide variety of application domains. It supports multiple programming paradigms.
• eSim 
  (formerly known as Oscad/FreeEDA) is an EDA tool for circuit design, simulation, analysis and PCB design. It is developed by the FOSSEE team at IIT Bombay 
• Osdag 
  free/libre and open-source software which allows the user to design steel structures using a graphical user interface. The GUI also provides 3D visualization of the designed component and images
• DWSIM 
  free/libre and open source CAPE-OPEN compliant chemical process simulator. Helps understand the behavior of Chemical Systems by using rigorous thermodynamic and unit operations models.
• OpenFOAM 
  free/libre and open source CFD toolbox useful to solve anything from complex fluid flows involving chemical reactions, turbulence and heat transfer, to solid dynamics and electromagnetics.
• OpenModelica 
  free/libre and open source environment based on the Modelica modelling language for modelling, simulating, optimising and analysing complex dynamic systems.
• OpenPLC 
  free/libre and open source Programmable Logic Controller creating opportunities for people to study its concepts, explore new technologies and share the resources.
• FLOSS-Arduino
  control of Arduino using Free/Libre Open-Source Software. The interface helps the user to perform embedded systems experiments on the Arduino Uno board.
• SBHS
  (Single Board Heater System) is a lab-in-a-box setup useful for teaching and learning control systems.
• R 
  programing language and environment for statistical computing and graphics.
• QGIS
  (Quantum GIS) is a free and open-source desktop Geographic Information System (GIS) application.
• FOCAL 
  an initiative by FOSSEE to promote Open Source Software in computer graphics.
• SOUL
  (Science OpensoUrce Software for Teaching Learning) is a collection of ICT software that can be used as teaching/learning tools by the community of educators and the learners to teach/ learn the basic as well as the advanced concepts in science subjects

[gnugen] Install Fest and Workshop git

Install Fest
Come discover Linux and if you want, we'll be ready to help you install it on your computer !
(remember to take a backup of your data before, just in case)

📅 When: this Saturday, 23th of march from 10h to 17h
📌 Where: EPFL CM 1 100

Workshop: just do git, at 13h30 if you'd like to learn how to use git for an efficient collaboration

[Habilitation] Assessment of novel devices in CMOS technology

Assessment of novel devices in CMOS technology

by electrical characterization and physics-based model

Habilitation Presented To Obtain The Authorization 

To Direct Research From Sorbonne University

Lionel Trojman, PhD

Sorbonne Université, 2020

Organization of the thesis

Chapter 1: This chapter extends research work after the author’s PhD study. It focuses on HfO2-based dielectric MOSFETs with sub-1nm EOT. The study explores the impact of transport factors like saturation velocity on planar MOSFETs and the mobility of FDSOI-UTBB MOSFETs. Notably, the back-biased effect is considered, and an inversion charge model is developed for different front and back biases.

Chapter 2: Emphasis the application of the statistical defect-centric model to assess the impact of channel hot carriers on the reliability of low-dimensional MOSFETs.

Chapter 3: This chapter shifts focus to GaN-on-Si wafer devices for power electronic applications. These devices integrate MOS-like structures into III-V material-based devices, specifically MOS-HEMT and GET-SBD.

Chapter 4: Investigates RERAM devices. It stems from cooperative research with UNICAL and a PhD program in collaboration with Aix-Marseille University

FIG: Description of the gate structure (half device) of the studied device including the parasitic capacitance inner fringing (CIF), outer fringe (COF) and Junction overlap capacitance (COV)

 

 

IEEE 5NANO2024 Conference 25-26th April, 2024

IEEE 5NANO2024

2024 IEEE International Conference on Nanoelectronics, Nanophotonics,
Nanomaterials, Nanobioscience & Nanotechnology

25th & 26th April 2024

VISAT Engineering College

Elanji, Ernakulam, Kerala, India - 686 665.

The IEEE 5NANO2024 International Conference is going to be dynamic and informative as it provides the premier interdisciplinary forum for researchers, practitioners and educators to present and discuss the most recent innovations, trends, practical challenges encountered, and the solutions adopted in the field of Nanotechnology. The theme of the conference is: “Future Challenges and Advanced Innovations in Nanotechnology”

Contact 5NANO2024:

Dr. T.D.Subash, Conference Organizing Chair - 5NANO2024,
VISAT Engineering College,
Elanji, Ernakulam, Kerala, India - 686 665

Tel: +91 9447691397, +91 9486881397.
E-mail: deanresearch@visat.ac.in, tdsubash2007@gmail.com, 5nano2k24@gmail.com

Website: https://www.5nano2024.com

[paper] in-memory computing using FeFET

Taha Soliman, Swetaki Chatterjee, Nellie Laleni, Franz Müller, Tobias Kirchner, Norbert Wehn, Thomas Kämpfe, Yogesh Singh Chauhan and Hussam Amrouch

First demonstration of in-memory computing crossbar using multi-level Cell FeFET

Nat Commun 14, 6348 (2023)

DOI: 10.1038/s41467-023-42110-y

1 Robert Bosch GmbH, Renningen, Germany
2 Semiconducture Test and Reliability, University of Stuttgart, Stuttgart, Germany
3 Department of Electrical Engineering, IIK, Kanpur, India
4 Fraunhofer IPMS, Dresden, Germany
5 RPTU Kaiserslautern-Landau, Kaiserslautern, Germany
6 MIRMI; Technical University of Munich, Germany

Abstract: Advancements in AI led to the emergence of in-memory-computing architectures as a promising solution for the associated computing and memory challenges. This study introduces a novel in-memory-computing (IMC) crossbar macro utilizing a multi-level ferroelectric field-effect transistor (FeFET) cell for multi-bit multiply and accumulate (MAC) operations. The proposed 1FeFET-1R cell design stores multi-bit information while minimizing device variability effects on accuracy. Experimental validation was performed using 28 nm HKMG technology-based FeFET devices. Unlike traditional resistive memory-based analog computing, our approach leverages the electrical characteristics of stored data within the memory cell to derive MAC operation results encoded in activation time and accumulated current. Remarkably, our design achieves 96.6% accuracy for handwriting recognition and 91.5% accuracy for image classification without extra training. Furthermore, it demonstrates exceptional performance, achieving 885.4 TOPS/W–nearly double that of existing designs. This study represents the first successful implementation of an in-memory macro using a multi-state FeFET cell for complete MAC operations, preserving crossbar density without additional structural overhead.

FIG: a.) The material stack of FeFETs. 

b.) The multi-bit FeFET can be programmed to different states

to store the weight of the synapse

Acknowledgements: This work has received funding from the ECSEL Joint Undertaking (JU) under grant agreement No 826655 and No 876925. The JU receives support from the European Union’s Horizon 2020 research and innovation programme and Belgium, France, Germany, Portugal, Spain, The Netherlands, Switzerland. Open Access funding enabled and organized by Projekt DEAL.

[paper] Symmetric BSIM-SOI

Chetan Kumar Dabhi, Dinesh Rajasekharan, Girish Pahwa, Debashish Nandi, Naveen Karumuri, Sreenidhi Turuvekere, Anupam Dutta, Balaji Swaminathan, Srikanth Srihari, Yogesh S. Chauhan, Sayeef Salahuddin, and Chenming Hu

Symmetric BSIM-SOI: A Compact Model for Dynamically Depleted SOI MOSFETs 

 in IEEE TED (2024)

Part I DOI: 10.1109/TED.2024.3363110

Part II DOI: 10.1109/TED.2024.3363117

1 Department of Electrical Engineering and Computer Sciences, UCB, CA, USA

2 Department of Electrical Engineering, IIT Kanpur, India

3 GlobalFoundries, Bengaluru, India

Abstract: In this article, we present a symmetric surface-potential-based model for dynamic depletion (DD) device operation of silicon-on-insulator (SOI) FETs for RF and analog IC design applications. The model accurately captures the device behavior in partial depletion (PD) and full depletion (FD) modes, as well as in the transition from PD to FD, based on device geometry, doping, and bias conditions. The model also exhibits an excellent source–drain symmetry during dc and small-signal simulations, resulting in error-free higher order harmonics. The model is fully scalable with bias, temperature, and geometry and has been validated extensively with real device data from the industry. The symmetric BSIM-SOI model is developed in Verilog-A and compatible with all commercial SPICE simulators.

FIG: (a) Schematic of a typical SOI MOSFET

(b) Cgg versus Vgb for different substrate bias, with the PD-to-FD transition 

Acknowledgment: The authors thanks the members of the Compact Model Coalition (CMC), particularly Geoffrey J. Coram and Jushan Xie, for testing the model and suggesting improvements. The authors appreciate the CMC QA team’s efforts in conducting a model quality check. Caixia Han and Xiao Sun from Cadence provided a few useful test cases. They thank Ananth Sundaram and Anamika Singh Pratiyush from GlobalFoundries India for the help and discussion regarding DDSOI model intricacies and development. Model code is available at BSIM Website <https://bsim.berkeley.edu/models/bsimsoi/>

SSCS April Technical Webinar

SSCS April Technical Webinar

Getting Started with Open Source Silicon, Presented By: Matthew Venn

Abstract: In this presentation, Matt Venn will share his experience of getting started with chip design using the free and open source tools. Going from zero to 20 chips in 3 years, there are plenty of successes and failures to share. Matt will then move on to sharing the best resources, inspirational example projects, and showcase some of his own tools. The presentation will finish with a demonstration showing just how easy and cheap it is to get your own chip manufactured today.

Biography: Matt Venn is a science & technology communicator and electronic engineer. He has been involved with open source silicon for the last 3 years and has sent 20 chips for manufacture. He has helped over 600 people learn the tools, with 300 people taking part in manufacturable designs:

• https://zerotoasiccourse.com/
• https://tinytapeout.com

Date: 2024-04-19 Time: 11 AM ET

Location Webinar - Online

Contact Aeisha VanBuskirk – a.vanbuskirk@ieee.org

Register Here

[paper] Topological Transistor Compact Model

Md. Mazharul Islam¹, Shamiul Alam¹, Md. Shafayat Hossain², Ahmedullah Aziz¹

Compact Model of a Topological Transistor

 IEEE Access; Feb.7, 2024

DOI: 10.1109/ACCESS.2024.3363645

1 Department of Electrical Engineering and Computer Science, The University of Tennessee, USA
2 Department of Physics, Princeton University, USA

Abstract: The precession of a ferromagnet leads to the injection of spin current and heat into an adjacent non-magnetic material. Besides, spin-orbit entanglement causes an additional charge current injection. Such a device has been recently proposed where a quantum-spin hall insulator (QSHI) in proximity to a ferromagnetic insulator (FI) and superconductor (SC) leads to the pumping of charge, spin, and heat. Here we build a circuit-compatible Verilog-A-based compact model for the QSHI-FI-SC device capable of generating two topologically robust modes enabling the device operation. Our model also captures the dependence on the ferromagnetic precision, drain voltage, and temperature with an excellent (>99%) accuracy.

FIG: (a) The proposed device structure. A QSHI in proximity with the FI with a monodomain magnetization m(t) that precesses at an angle θ. In proximity to the FI region there is a SC region The monodomain magnetization m(t) precesses at an angle θ around the axis perpendicular to the QSHI. The QSHI region injects charge, spin, and heat currents to the drain. The injection can be controlled by the applied potential at the FI region (Vg), the precession angle (θ), precession frequency (ω) temperature (T) and drain voltage (Vd ). Zero energy Majorana Fermion (MF) is harbored in the FI-SC interface that controls the pumped currents. (b) Circuit schematics for our simulation process. (c) Methodology flow for compact modeling

Acknowledgement: This work was supported by the Air Force Research Laboratory under Agreement FA8750-21-1-1018.

[paper] Next Wave for AI/ML in Physical Design

Andrew B. Kahng

Solvers, Engines, Tools and Flows: The Next Wave for AI/ML in Physical Design

ISPD ’24 Proceedings

March 12–15, 2024, Taipei, Taiwan.

DOI 10.1145/3626184.3635277

Abstract: It has been six years since an ISPD-2018 invited talk on “Machine Learning Applications in Physical Design”. Since then, despite considerable activity across both academia and industry, many R&D targets remain open. At the same time, there is now clearer understanding of where AI/ML can and cannot (yet) move the needle in physical design, as well as some of the difficult blockers and technical challenges that lie ahead. Some futures for AI/ML-boosted physical design are visible across solvers, engines, tools and flows and in contexts that span generative AI, the modeling of “magic” handoffs at flow interstices, academic research infrastructure, and the culture of benchmarking and open-source EDA.

Fig: OpenROAD as a new EDA playground for ML researchers

Acknowledgments: Many thanks to Sayak Kundu, Bodhisatta Pramanik, Zhiang Wang and Dooseok Yoon for their help with the figures and text in this paper. Discussions with Siddhartha Nath, Igor Markov, Chuck Alpert and Ilgweon Kang are also gratefully acknowledged. Research at UCSD is partially supported by DARPA, Samsung, the C-DEN center, and gifts from Google, Intel and others.

Importance of Open-Source EDA Tools for Academia

Importance of Open-Source EDA Tools for Academia

Open Letter on European Strategic and Funding Directions

https://open-source-eda-letter.eu/

Initial Signatories of the Open-Source-EDA-Letter, as of March 8, 2024, are:

Luca Benini
University of Bologna, Italy & ETH Zürich, Switzerland
Professor, Lead of the RISC-V PULP platform

Giovanni De Micheli
EPFL Lausanne, Switzerland
Professor and Director, LSI lab

Marie-Minerve Louërat
Sorbonne University, France

Research Scientist, Coriolis Foundation hosted by CNRS Foundation

Harald Pretl
Johannes Kepler University Linz, Austria
Professor, Maintainer of IIC-OSIC-TOOLS

Stefan Wallentowitz
Hochschule München University of Applied Sciences, Germany
Professor, Director at FOSSi Foundation & Director at RISC-V

All the educators and researchers from European academic institutions are kindly asked to consider and eventually co-sign this open letter. To co-sign, please send a mail from your university mailing address to stefan.wallentowitz@hm.edu and include your affiliation and ideally include a link to your profile.

AACD 2024 Final Program

We are proud to announce the final program

of the 32nd Advances in Analog Circuit Design Workshop (AACD24),

which will be held at University of Pavia, Italy on April, 9th-11th, 2024

---

Registration to AACD24 is open at:

https://www.mbtechnoservices.com/aacd24/index.php?page=Registration.html

---

Registration to AACD24 is open at:
https://www.mbtechnoservices.com/aacd24/index.php?page=Registration.html

For any further information:

• Visit http://www.mbtechnoservices.com/aacd24
• Contact the AACD24 Organizing Committee: Andrea Baschirotto (andrea.baschirotto@unimib.it), Piero Malcovati (piero.malcovati@unipv.it)

We look forward to meeting you in Pavia for this very exciting edition of the AACD Workshop!!!!

Andrea Baschirotto
Piero Malcovati AACD24 Organizing Committee

Please do not reply to this e-mail. If you want to be removed from the MBTechnoServices mailing list, please visit: http://www.mbtechnoservices.com/index.php?page=MailingList/Unsubscribe.html&EMail=wladek@mos-ak.org

[Open PDK] IEEE EDS DL at IISc Banglare

IEEE EDS/SSCS Bangalore Chapter Presents DL Series

FOSS TCAD/EDA Tools SPICE and Verilog-A

Modeling Flow Technology - Devices - Applications

W.Grabinski, MOS-AK (EU)

DATE AND TIME	LOCATION	HOSTS
Date: 07 Mar 2024 Time: 04:00 PM to 05:00 PM All times are (UTC+05:30) Chennai Add Event to Calendar iCal Google Calendar	Auditorium, Dept. of ESE, IISc Bangalore Karnataka India 560012	Bangalore Section Jt. Chapter ED15/SSC37

[EDTM] Open PDK Initiative

8th IEEE EDTM

March 3-6, 2024

Strengthening Globalization in Semiconductors

The EDTM Conference to host two contributions discussing the status of Open PDK Initiative:

[6C-1] [Invited] Disrupting Conventional Chip Design through the Open Source EDA Ecosystem
Mehdi Saligane; University of Michigan, USA

[P2-36] FOSS CAD for the Compact Verilog-A Model Standardization in Open PDKs
Wladek Grabinski, et al. MOS-AK (EU); IHP - Leibniz-Insitut für innovative Mikroelektronik;

as of March 12, 2024:

 

[EDTM] Inauguration Session

8th IEEE EDTM

March 3-6, 2024

Strengthening Globalization in Semiconductors

The 8th Electron Devices Technology and Manufacturing Conference (IEEE EDTM 2024) will be held for the first time in India at Bangalore; the Silicon Valley of India and the hub of semiconductor companies. IEEE EDTM 2024 will be a full four-day conference to be held during March 3-6, 2024. IEEE EDTM 2024 aims to be a premier global forum for researchers and engineers from around the world coming to share new discoveries and discuss any device/manufacturing-related topics, including but not limited to, materials, processes, devices, packaging, modeling, reliability, manufacturing and yield, tools, testing, and any emerging device technologies, as well as workforce training. 

Plenary Talk by Prof. Chenming Hu "Semiconductor – the Next 75 Years?"