[OSDA 2024] 4th Workshop on Open-Source Design Automation

4th Workshop on Open-Source Design Automation

OSDA 2024

at DATE Palacio De Congresos València, Spain

25 Mar 2024

Organiser: Christian Krieg, TU Wien, Austria

OSDA intends to provide an avenue for industry, academics, and hobbyists to collaborate, network, and share their latest visions and open-source contributions, with a view to promoting reproducibility and re-usability in the design automation space. DATE provides the ideal venue to reach this audience since it is the flagship European conference in this field -- particularly poignant due to the recent efforts across the European Union (and beyond) that mandate “open access” for publicly funded research to both published manuscripts as well as software code necessary for reproducing its conclusions. A secondary objective of this workshop is to provide a peer-reviewed forum for researchers to publish “enabling” technology such as infrastructure or tooling as open-source contributions -- standalone technology that would not normally be regarded as novel by traditional conferences -- such that others inside and outside of academia may build upon it.

Agenda:

Christian Krieg; Post-Doctoral Researcher and Teacher at TU Wien

Welcome Session

Luca Carloni ;Professor at Columbia University

ESP: An Open-Source Platform for Collaborative Design of Heterogeneous Systems-on-Chip

Jean-Paul Chaput; Engineer at Sorbonne Université

Update on the Coriolis EDA Toolchain

Dirk Koch; Professor at Heidelberg University

FABulous: An embedded eFPGA Framework - an Update

Matthew Venn; Founder at YosysHQ, TinyTapeout

Demo Pitch: Tiny Tapeout

Claire Xenia Wolf; CTO at YosysHQ

Yosys

Frans Skarman PhD Student at Linköping University

Surfer -- An Extensible and Snappy Waveform Viewer

Poster Session

• Vojtech Mrazek
  An Open-Source Automated Design Space Exploration Framework for Approximate Accelerators in FPGAs and ASICs
• Marc Solé i Bonet, Aridane Alvarez Suarez and Leonidas Kosmidis
  The METASAT Hardware Platform v1.1: Identifying the Challenges for its RISC-V CPU and GPU Update
• Louis Ledoux and Marc Casas
  The Grafted Superset Approach: Bridging Python to Silicon with Asynchronous Compilation and Beyond
• Manfred Schlägl, Christoph Hazott and Daniel Große
  RISC-V VP++: Next Generation Open-Source Virtual Prototype
• Guillem López-Paradís, Brian Li, Adrià Armejach, Stefan Wallentowitz, Miquel Moretó and Jonathan Balkind
  Using Supercomputers to Parallelize RTL Simulations
• Davide Cieri
  Hog (HDL on git): a tool to manage HDL code on a git repository
• Jakob Ratschenberger and Harald Pretl
  RALF: A Reinforcement Learning Assisted Automated Analog Layout Design Flow
• Ajeetha Kumari Venkatesan, Anirudh Pradyumnan Srinivasan, Deepa Palaniappan
  Adding configurability to PySlint using TOML
• Lucas Klemmer and Daniel Grosse
  WSVA: A SystemVerilog Assertion to WAL Compiler