Showing posts with label Verilog-A; SPICE-like simulators; code generators; compact models. Show all posts
Showing posts with label Verilog-A; SPICE-like simulators; code generators; compact models. Show all posts
Jan 30, 2013

Why- and how- to integrate Verilog-A compact models in SPICE simulators

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Article first published online: 20 JUL 2012 by Maria-Anna Chalkiadaki1, Cédric Valla2, Frédéric Poullet2 and Matthias Bucher1 (1. Departmen...