Showing posts with label
Verilog-A analogue module synthesis
.
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Showing posts with label
Verilog-A analogue module synthesis
.
Show all posts
Apr 19, 2016
[mos-ak] A new approach to compact semiconductor device modelling with Qucs Verilog-A analogue module synthesis
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A new approach to compact semiconductor device modelling with Qucs Verilog-A analogue module synthesis M. E. Brinson 1,* andV. Kuzne...
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