Showing posts with label
Ferroelectric
.
Show all posts
Showing posts with label
Ferroelectric
.
Show all posts
Jul 26, 2021
[paper] NCFET CMOS Logic
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Reinaldo Vega, Senior Member, IEEE, Takashi Ando*, Senior Member, IEEE, Timothy Philip, Member, IEEE Junction Design and Complementary Cap...
Jul 17, 2020
[paper] Compact Modeling of NC FDSOI FETs
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C. K. Dabhi, S. S. Parihar, A. Dasgupta and Y. S. Chauhan Compact Modeling of Negative-Capacitance FDSOI FETs for Circuit Simulations I...
Jun 17, 2020
[paper] Compact Model for Ferroelectric FET
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Lu, Darsen, Sourav De, Mohammad Aftab Baig, Bo-Han Qiu, and Yao-Jen Lee Computationally efficient compact model for ferroelectric field-e...
May 1, 2020
[paper] Physical Mechanisms of Reverse DIBL and NDR in FeFETs With Steep Subthreshold Swing
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C. Jin, T. Saraya, T. Hiramoto and M. Kobayashi, in IEEE J-EDS, vol. 8, pp. 429-434, 2020 doi: 10.1109/JEDS.2020.2986345 Abstract - ...
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