Showing posts with label
Double-Gate (DG) Tunnel-FET
.
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Showing posts with label
Double-Gate (DG) Tunnel-FET
.
Show all posts
Feb 22, 2018
[paper] TFET Devices Re-Evaluation Résumé
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Capturing Performance Limiting Effects in Tunnel-FETs Michael Graef 1,2 , Fabian Hosenfeld 1,2 , Fabian Horst 1,2 , Atieh Farokhnejad 1,2 ...
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