Showing posts with label
3D logic circuit cell
.
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Showing posts with label
3D logic circuit cell
.
Show all posts
Jul 26, 2021
[paper] VNWFET Including Tied Compact Model
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Arnaud Poittevin1, Chhandak Mukherjee2, Ian O’Connor1, Cristell Maneux2, Guilhem Larrieu3,4, Marina Deng2, Sebastien Le Beux1, Francois Marc...
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