Showing posts with label
2D-2D tunneling
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Showing posts with label
2D-2D tunneling
.
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Oct 2, 2017
[paper] A Novel Reconfigurable sub-0.25V Digital Logic Family Using the Electron-Hole Bilayer TFET
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Cem Alper, Jose Luis Padilla, Pierpaolo Palestri, Senior Member, IEEE and Adrian M. Ionescu, Fellow, IEEE IEEE Journal of the Electron ...
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