We are glad to inform you that the IEEE Student Branch MNIT Jaipur in association with IEEE EDS Student Branch Chapter MNIT Jaipur is organizing an invited talk on ''FOSS TCAD/EDA Tools SPICE and Verilog-A Modeling Flow'' by Dr Wladek Grabinski, R&D SPICE Manager, MOS-AK (EU)
There is no registration fee, however prior registration is required. This invited talk will be held in online mode.
E-certificate will be provided to all registered participants.
Title: ''FOSS TCAD/EDA Tools SPICE and Verilog-A Modeling Flow"
Abstract:Compact/SPICE models of circuit elements (passive, active, MEMS, RF, Microwave, Photonics) are essential to enable advanced IC design using nanoscaled semiconductor technologies. Compact/SPICE models are also a communication means between the semiconductor foundries and the IC design teams to share and exchange all engineering and design information. To explore all related interactions, we are discussing selected FOSS CAD tools along the complete technology/design tool chain from nanascaled technology processes; thru the compact modeling; to advanced IC transistor level design support. New technology and device development will be illustrated by application examples of the FOSS TCAD tools: Cogenda TCAD and DEVSIM. Compact modeling will be highlighted by review topics related to its parameter extraction and standardization of the experimental and measurement data exchange formats. Application and use of these tools for advanced IC design (e.g. analog/RF, Microwave, Photonics applications) directly depends on the quality of the compact model implementations in these tools as well as reliability of extracted models and generated libraries/PDKs. Discussing new model implementation into the FOSS CAD tools (Gnucap, Xyce, ngspice and Qucs as well as others) we will also address an open question of the compact/SPICE model Verilog-A standardization. We hope that this presentation will be useful to all the researchers and engineers actively involved in the developing compact/SPICE models as well as designing the integrated circuits in particular at the semiconductor device level and then trigger further discussion on the compact/SPICE model Verilog-A standardization and development supporting FOSS CAD tools.
Registration Link:
https://forms.gle/xnkEo2i92UzdjK5PA
Joining Link:
http://meet.google.com/cpd-mopg-eea
Date: 22nd September 2022
Time: 03:00-04:00 PM IST
We are looking forward to active participation from your side.
Girdhar Gopal
Research Scholar, MNIT Jaipur
Chair, Student Branch Chapter
MNIT, Jaipur
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