[paper] Compact Model of JLNGAA MOSFET in Verilog-A

Billel Smaani^1,2, Shiromani Balmukund Rahi³ and Samir Labiod⁴

Analytical Compact Model of Nanowire Junctionless Gate-All-Around MOSFET

Implemented in Verilog-A for Circuit Simulation. 

Silicon (2022)

DOI: 10.1007/s12633-022-01847-9

   

1 Centre Universitaire Abdelhafid Boussouf, Mila, Algeria

2 Electronique Department, Constantine I University, Algeria

3 Department of Electrical Engineering, IIT Kanpur, India

4 Department of Physics, Skikda University, Algeria

Abstract: In the present research article, we have proposed an analytical compact model for Nanowire Junctionless Gate-All-Around (JLNGAA) MOSFET validated in all transistor’s operation regimes. The developed model having an analytical compact form of the current expressions, based on surface potential (ΦS), obtained from approximated solutions of Poisson’s equation. The proposed model has implemented in standard Verilog-A language using SMASH circuit simulator in order to be used in various commercial circuit simulators. The proposed model has also validated using ATLAS-TCAD simulation for various physical parameters such as the channel doping concentration (Nd) and the channel radius (R) of JLNGAA MOSFET. Finally, based on the developed Verilog-A JLNGAA MOSFET model, we have tested it in four types of low voltage circuits, CMOS inverter, CMOS NOR-Gate, an amplifier and a Colpitts oscillator.

Fig: Transient simulation of the implemented Colpitts oscillator using SMASH, where Vout is the output voltage. R = 4 nm, tox = 2 nm, L = 1 μm and Nd = 1E19/cm^3

Acknowledgments: Dr. S. B. Rahi (Indian Institute of Technology, Kanpur, India) for their useful suggestions