[paper] Charge Trapping/Detrapping in Scaled MOSFETs

Ruben Asanovski, Pierpaolo Palestri*, and Luca Selmi

Importance of Charge Trapping/Detrapping Involving the Gate Electrode on the Noise Currents of Scaled MOSFETs

IEEE TED, Vol. 69, No. 3, March 2022 1313

DOI: 10.1109/TED.2022.3147158

  

 Università degli Studi di Modena e Reggio Emilia, Modena, Italy

*Università degli Studi di Udine, Udine, Italy

Abstract: Carrier trapping/detrapping from/to the gate into dielectric traps is often neglected when modeling noise in MOSFETs and, to the best of our knowledge, no systematic study of its impacts on scaled devices is available. In this article, we show that this trapping mechanism cannot be neglected in nowadays aggressively scaled gate dielectric thicknesses without causing errors up to several orders of magnitude in the estimation of the drain current noise. The noise generation mechanism is modeled analytically and then analyzed through the use of 2-D and 3-D TCAD simulations of scaled MOSFETs with different architectures and channel/gate-stack materials. The results provide new insights for technology and device designers, highlight the relevance of the choice of the gate metal work function (WF) and the role of valence band electron trapping at high gate voltages.

Fig: (a) FinFET with the single trap location highlighted. (b) Drain current noise comparison between TCAD simulations at VGS = 0.7 V, VDS = 25 mV and single trap located as in (a).