Sedemos News: 8th EuroSOI-ULIS 2022 at University of Udine (Italy)

Organized by:
University of Udine (Italy)

Conference chair:

Pierpaolo Palestri

Local organizing Committee:

Francesco Driussi
David Esseni
Daniel Lizzit

Conference Secretariat:
Centro Congressi Internazionali

Steering Committee:

Francis BALESTRA
(IMEP Minatec, France)
Maryline BAWEDIN
(IMEP-LAHC, France)
Cor CLAEYS
(KU-Leuven, Belgium)
Bogdan CRETU
(ENSICAEN, France)
Sorin CRISTOLOVEANU
(IMEP-LAHC, France)
Francisco GAMIZ
(UnivGranada, Spain)
Elena GNANI
(Univ. of Bologna, Italy)
Benjamin INIGUEZ
(URV, Spain)
Joris LACORD
(CEA-Leti, France)
Enrico SANGIORGI
(Univ.Bologna, Italy)
Luca SELMI
(Univ. of Modena, Italy)
Viktor SVERDLOV
(TU Wien, Austria)
Andrei VLADIMIRESCU
(ISEP, France)

Sponsors:

8th Joint International EuroSOI Workshop and International Conference
on Ultimate Integration on Silicon (EuroSOI-ULIS) 2022
May 18-20, 2022 – Udine, Italy
https://eurosoiulis2022.com

The Conference aims at gathering together scientists and engineers working in academia, research centers and industry in the field of SOI technology and nanoscale devices in More-Moore and More-Than-Moore scenarios. High quality contributions in the following areas are solicited:

Advanced SOI materials and structures, innovative SOI-like devices.
Alternative transistor architectures (FDSOI, Nanowire, FinFET, MuGFET, vertical MOSFET, FeFET and TFET, MEMS/NEMS, Beyond-CMOS).
New channel materials for CMOS (strained Si/Ge, III-V, carbon nanotubes; graphene and other 2D materials).
Properties of ultra-thin semiconductor films and buried oxides, defects, interface quality; thin gate dielectrics: high-κ and ferroelectric materials for switches and memory.
New functionalities and innovative devices in the More than Moore domain: nanoelectronic sensors, biosensor devices, energy harvesting devices, RF devices, imagers, integrated photonics (on SOI), etc.
Transport phenomena, compact modeling, device simulation, front- and back-end process simulation.
CMOS scaling perspectives; device/circuit level performance evaluation; switches and memory scaling; three-dimensional integration of devices and circuits, heterogeneous integration.
Advanced test structures and characterization techniques, parameter extraction, reliability and variability assessment techniques for new materials and novel devices.

Original 2-page abstracts with illustrations will be reviewed by the Scientific Committee. The accepted contributions will be published as 4-page letters in a special issue of the Elsevier journal Solid-State Electronics. Extended versions of outstanding papers will be published in a further special issue of Solid-State Electronics. A best poster award will be attributed by ELSEVIER.

The “Androula Nassiopoulou Best Paper Award"

will be attributed by the SINANO institute.

Important dates: