[paper] Nanosheet field effect transistors

J. Ajayan^a, D. Nirmal^b, Shubham Tayal^a, Sandip Bhattacharya^a, L. Arivazhagan^c, A.S. Augustine Fletcher^b, P. Murugapandiyan^d, D. Ajitha^e

Nanosheet field effect transistors - A next generation device to keep Moore’s law alive:
An intensive study

Microelectronics Journal 114 (2021) 105141

DOI: 10.1016/j.mejo.2021.105141

a SR University, Warangal, Telangana, India
b Karunya Institute of Technology and Sciences, Coimbatore, Tamilnadu, India
c Sri Ramakrishna Engineering College, Coimbatore, Tamilnadu, India
d Anil Neerukonda Institute of Technology & Sciences, Visakhapatnam, Andhra Pradesh, India
e Sreenidhi Institute of Science and Technology, Hyderabad, Telangana, India

Abstract: Incessant downscaling of feature size of multi-gate devices such as FinFETs and gate-all-around (GAA) nanowire (NW)-FETs leads to unadorned effects like short channel effects (SCEs) and self-heating effects (SHEs) which limits their performance and causes reliability issues. FinFET technology has resulted in a remarkable performance up to a feature size of 7nm. The research community is expecting that GAA NW-FETs will take over FinFET technology from 7nm to 5nm. However, further shrinking of feature size to 3nm will impose severe challenges to the performance of these aforesaid multi-gate devices. Subsequently, the electron device designer community needs to look for alternative device designs like nanosheet FETs (NS-FETs) to overcome the limitations of the FinFET and GAA NW-FETs technologies. The driving force behind the emergence of these NS-FETs is their ability to scale down even below a feature size of 5nm with negligible short channel effects. Therefore, in this review article we have intensively investigated the NS-FETs in terms of impact of geometrical scaling, substrate material effects, parasitic channel effects, thermal effects, compatibility with different metal gates, and source/drain (S/D) metal depth effect. Consequently, it can be concluded that vertically stacked NS-FET is the most promising solution for future digital/analog integrated circuit applications due to their outstanding capability to keep Moore’s Law alive.

Fig: 3-D views of (a) FinFET (b) stacked NW-FET (c) vertically stacked NSFET.