[paper] Compact Modeling of Flicker Noise in HV MOSFETs

Ravi Goel (Student Member, IEEE), Yogesh Singh Chauhan (Fellow, IEEE) 

Compact Modeling of Flicker Noise in High Voltage MOSFETs and Experimental Validation 

In 2021 IEEE Latin America Electron Devices Conference (LAEDC), pp. 1-4. IEEE, 2021 

DOI: 10.1109/LAEDC51812.2021.9437922

*Department of Electrical Engineering, Indian Institute of Technology Kanpur, India

Abstract: An analytical model of flicker noise (also called 1/f or low frequency noise) for the drift region is developed to formulate a 1/f model for high voltage MOSFETs using the subcircuit approach in this work. For halo doped drain extended MOSFET (DEMOS), the contribution factors of halo, channel and drift regions are obtained to capture anomalous behavior of 1/f noise. Similar to Halo doped DEMOS, for LDMOS, the contribution factors for channel and the drift region are obtained to capture the SID for different drain biases and channel lengths. The proposed model is validated with measurement data of 50V LDMOS and DEMOS.

Fig: Halo doped DEMOS and its sub-circuit equivalent. In halo doped DEMOS, the channel is divided into halo region and channel region, followed by drift region. In LDMOS, the channel is followed by the drift region. CFsh, CFch, and CFdrift are the contribution factors and are calculated using small-signal analysis.

Acknowledgments: The authors thank Sarvesh S. Chauhan for his valuable feedback. This work was partially supported by the Swarna Jayanti Fellowship (Grant No. – DST/SJF/ETA-02/2017- 18) and FIST Scheme (Grant No. – SR/FST/ETII-072/2016) of the Department of Science and Technology, India and Berkeley Device Modeling Center (BDMC).