[paper] Vertical III-V Nanowire MOSFETs on Si

Olli-Pekka Kilpi, Markus Hellenbrand, Johannes Svensson, Axel R. Persson, Reine Wallenberg, Erik Lind, Member, IEEE, and Lars-Erik Wernersson

High-Performance Vertical III-V Nanowire MOSFETs on Si With gm > 3 mS/μm

in IEEE EDL vol. 41, no. 8, pp. 1161-1164, Aug. 2020

DOI: 10.1109/LED.2020.3004716

Abstract: Vertical III-V nanowire MOSFETs have demonstrated excellent performance including high transconductance and high Ion. One main bottleneck for the vertical MOSFETs is the large access resistance arising from the contacts and ungated regions. We demonstrate a process to reduce the access resistance by combining a gate-last process with ALD gate-metal deposition. The devices demonstrate fully scalable gm down to Lg = 25 nm. These vertical core/shell InAs/InGaAs MOSFETs demonstrate gm = 3.1 mS/μm and Ron = 190 μm. This is the highest gm demonstrated on Si. Transmission line measurement verifies a low contact resistance with RC = 115 μm, demonstrating that most of the MOSFET access resistance is located in the contact regions.

FIG: (a) of the MOSFET structure demonstrating benefit of the TiN gate metal;

(b )output characteristics of the vertical nanowire MOSFET 

with 90 nanowires, LG = 25 nm and diameter 17 nm.

Acknowledgment: This work was supported in part by the Swedish Research Council, in part by the Knut and Alice Wallenberg Foundation, in part by the Swedish Foundation for Strategic Research, and in part by the European Union H2020 Program INSIGHT under Grant 688784.