[paper] compact nanowire JAM-MOSFET model

Kamalaksha Baral, Prince Kr Singh, Sanjay Kumar, Manas Ranjan Tripathy,

Ashish Kr Singh, Sweta Chander and S JitA

2-D compact DC model for engineered nanowire JAM-MOSFETs 

valid for all operating regimes

Semiconductor Science and Technology, Vol. 35, No. 8

Abstract: This manuscript reports a 2-D compact analytical model for DC characteristics under all possible regimes of operations of a cylindrical gate (CG) nanowire junctionless accumulation mode (JAM) MOSFET including the effects of various device engineering techniques. Superposition technique with appropriate boundary conditions has been used to solve 2-D Poisson’s equation considering both free/accumulation and depletion charges. The minimum potential concept has been used to conceive the threshold voltage formulation considering the effects of structural and electrical quantum confinements. An optimized device model has been formulated incorporating various device engineering. The potential model could also be used for potential modeling of doped inversion mode MOSFETs. Complete drain current including gate induced drain leakage (GIDL) has been derived from the potential model. Drain current has been derived individually for different regions. Further the effects of temperature and trapped interface charges have been included in the model. A 3-D commercial TCAD has been used to validate the model results of our proposed device. 

Fig: A 2-D cross-sectional view of cylindrical gate nanowire
junctionless accumulation mode MOSFET