[C4P] ESSDERC TRACK3 Compact Modeling

European ESSDERC/ESSCIRC conference will be organized in Grenoble (F) on Sept.14-18, 2020 with its integral TRACK3: Compact Modeling and Process/Device Simulation which is open for submissions, now. You and all your R&D partners are welcome to submit a modeling paper. The paper submission deadline is April 17, 2020

TRACK3: Compact modeling and process/device simulation (including TCAD and advanced simulation techniques and studies)  focuses on following domains among other R&D topics:

• Compact/SPICE modeling of electronic, optical, organic, and hybrid devices and their IC implementation and interconnection. 
• Verilog-A models of the semiconductor devices (including Bio/Med sensors, MEMS, Microwave, RF, HV and Power, emerging technologies and novel devices)
• Compact/SPICE parameter extraction
• Performance evaluation and open source (FOSS) benchmarking/implementation methodologies
• Modeling of interactions between process, device and circuit design, 
• Foundry/Fabless interface strategies
• Numerical TCAD, analytical, statistical modeling and simulation of electronic, optical and hybrid devices, interconnect, isolation and 2D/3D integration
• Aspects of materials, fabrication processes and devices e.g. advanced physical phenomena (quantum mechanical and non-stationary transport phenomena, ballistic transport, ...)
• Optical, mechanical or electro-thermal modeling and simulation
• DfM, ageing, reliability of materials and devices

Please share our TRACK3 C4P with all your academic and industrial R&D partners active in the compact/SPICE modeling, Verilog-A standardization and TCAD/EDA simulations. Of course, your and your research team proactive contribution to our TRACK3 is more than welcome. I do hope that despite of a last minute notice, with your help, we will be able to draw even more attention to the ESSDERC/ESSCIRC Conference and, in particular, our modeling TRACK3

-- ESSDERC TRACK3 TPC