Date: Sept 14th, 2010
Location: National Semiconductor, Building E1, Conference Center, 2900 Semiconductor Drive, Santa Clara , CA 95051 .
Abstract: A key device that is used in most high voltage (20 to 120V) power integrated circuits for power management applications is the Lateral Diffused MOS (LDMOS) transistor. Recent interest in ‘green” products have further increased the demand for integrated HV LDMOS devices in CMOS and BCD technologies to build higher efficiency dc-dc converters for consumer and LED markets. This presentation will journey through the structural innovations from “planar” to “trench” and to state-of-the-art “RESURF” LDMOS devices in both junction and dielectric isolation technologies for the past two decades. The physics of operation, figure of merits used for device comparison, layout techniques including integration of LDMOS into modern CMOS/BCD technologies will be discussed. Device and process simulations to optimize device parameters including SPICE macro circuits to model “quasi-saturation” and “Cgd” capacitance will be described. Methods to improve hot carrier reliability and ESD robustness of LDMOS devices will be highlighted. Finally, LDMOS circuit topologies and their applications in consumer, computer and telecommunication products will be presented to let the audience comprehend and appreciate the significance of LDMOS devices to modern power management products.
Web link: http://www.ewh.ieee.org/r6/scv/eds/
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