Agilent-EEsof X-Parameters Course

Agilent-EEsof is offering an 3-day course – July 7-9 (Massy – France)

WHAT WILL YOU LEARN?

• This course starts with an overview of non-linear components behavioral modeling and the extension of S-parameters into X-parameters.
• Then it drives you through the calibration requirements for X-parameters measurements. Finally the use of X-parameters models in ADS (Advanced Design System) is illustrated with cascaded amplifiers in an LTE (3rd Gen. Partnership Project - Long Term Evolution) RF subsystem.
• Participants will have the opportunity to drive the measurements and perform hands-on exercises in the ADS software.

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Organic, Molecular and Nanostructured Electronics - Physics and Technology

Date: June 8-12, 2009 | Continuing Education Units

Description: This course will review basic concepts underlying the design, fabrication, and operation of three dominant types of organic electronic devices: light emitting devices (OLEDs), photosensitive devices (solar cells and photodetectors), and field effect transistors (OFETs). We will also discuss, but devote less time to, organic lasers, organic memories, and chemical sensors. The course aims to present a broad and practical survey of the field and to immerse you in the broad field of organic materials. As a sub-class of nanostructured solids, organic thin films exemplify challenges of the practical nanotechnologies. Many concepts presented in the class are directly transferable to a broader field of nanostructured materials.

Instructors: Professors Vladimir Bulovic and Marc Baldo of the MIT Laboratory of Organic Optics and Electronics.

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International Summer School MOMiNE 2009

International Summer School on Modelling and Optimization in Micro- and Nano- Electronics - MOMiNE Italy Sept. 2009: The aim of the School is to stimulate intensive transfer of knowledge and discussion on modeling and optimization of electronic circuits and devices, by presenting the latest developments, insights, methods, algorithms and ideas in these areas of research, providing also indications for future research directions. An important aspect is the involvement of researchers working for industries, which can provide a more timely indication of the most relevant up-to-date problems encountered in real industrial environments.

The International Summer School MOMINE 2009 will be held from 31/08 to 12/09 at:

Grand Hotel San Michele
Località: Bosco 8/9, 87022 Cetraro (Cosenza), Italy
Phone: (+39) 0982 91012 Fax: (+39) 0982 91430

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Graduate Student Meeting on Electronic Engineering

The Graduated Student Meeting on Electronic Engineering (formerly Nanoelectronics and Photonics Systems Workshop), has been an annual event, created and organized by the Universitat Rovira i Virgili (URV), in Tarragona (Catalonia, Spain) since 2003. It consists of two days of plenary talks given by invited prestigious researchers (from different countries) about selected topics related to electronic engineering and two poster sessions were PhD students in this field will present their work.

This Graduated Student Meeting has become a very useful forum for PhD students and researchers in the field of Electronic Engineering. The present edition will take place in June 19th and 20th.

This year, the Graduated Student Meeting is being sponsored by the NANOSIL European Network of Excellence.

Awards for the best student paper/posters in two categories: one category for Master students and another category for Doctoral Students.

2-pages abstracts corresponding to paper or poster presentations and plenary talks will be published in the Proceedings. The deadline for abstracts reception is June 8th.

The plenary talks will be given by the following lecturers:

Prof Juin J Liou. University of Central Florida, Orlando, FL (USA). "Protecting Microchips agains Electrostatic Discharge (ESD) Shock."

Dr Michele Penza. Italian Agency for New Technologies, Energy and Environment.
Department of Physical technologies and new materials. Research Center Brindisi (Italy). "Carbon nanotube gas sensors: chemiresistors and SAW devices."

Prof. Ettore Napoli. Department of Electronic and Telecommunication Engineering. University of Naples Federico II (Italy). "Superjunction power devices".

Dr Denis Buttard. CEA-GrenobleLaboratoire de Silicium Nanoélectronique Photonique et StructuresINAC/SP2M/SiNaPSMINATEC-BCA. 38054 Grenoble Cedex 9 (France). "Elaboration and structural investigation of the confined growth of silicon nanowires in a nanoporous matrix: application to phovoltaic cell".

Prof. Yuhua Cheng. Shanghai Research Institute of Microelectronics, Peking University (China). "Design-for-Manufacturing in Nano-CMOS Era."

Dr. Daniela Iacopino. Nanotechnology Group. Tyndall National Institute. Cork (Ireland).
"Nanocrystal-Molecule Nanostructures: Formation, Plasmonic Properties & Electrical Contacting"

Tarragona is located in the south of Catalonia, in the northeast corner of the Iberian Peninsula.
Tarraco (the Roman name for Tarragona) was one of the most important cities in the Roman Empire. On 30 November 2000, the UNESCO committee officially declared the Roman archaeological complex of Tàrraco a World Heritage Site. This recognition is intended to help ensure the conservation of the monuments, as well as to introduce them to the broader international public.

In June the weather is warm enough to go to the beaches in or around Tarragona, but comfortable enough to walk and do sightseeing in the city. Thanks to its Mediterranean climate, its clean beaches with fine and gloden sand, and its singular artistic and architectural heritage, Tarragona is one of the most important tourism hubs in Europe.

I encourage Ph D students to send abstracts and attend this interesting Meeting!

Job offer in Compact Modelling - 28 May 2009

I post here a job offer from LinkedIn, I think it may be of interest for many of you, dearest readers.... Please remember that we only copy here the offer, and that we are not related in any way to those offering the position!!
In case you are interested, kindly pass your CV immediately to gopal.svks@gmail.com / gopal@svcircuit.com

Senior Manager/Manager -Analog-RF,AMS–Malaysia
Exp-PhD / Master with 10+ , candidate should be solid in Analog,RF characterization, SPICE & compact modeling for high voltage MOS, BJT, BCD devices

Placement location –Malaysia
Position -- very urgent and need to be filled ASAP.
Interview - 2weeks altogether.
Package – Will be the best in the semiconductor industry
Type -Full time and permanent with our client..


Malaysia Responsibilities:
• Lead a team of engineers to provide Integrated Circuit Design Technology solutions.
• Supervise test-chip design for "Client" technology characterization, SPICE model generation
for RF, Analog and mixed signal active and passive devices, and development of process design
kit (PDK) for "Client" technologies.
• Review, update, and manage electrical design rule (EDR) specifications for all "Client"
technologies – accuracy and availability of up-to-date revision.
• Interface with "Client" technology development (TD), customer engineering (CE), and Fab
engineering departments to support technology development, customer support, and
manufacturing, respectively.
• Interact with marketing group to provide modeling solutions to "Client" customers.
• Follow and comply with the procedures and by-laws of "Client" Environmental Management
System (EMS).
• Review all environmental objectives, targets, and plans and ensure their implementation in
accordance to the requirements set by "Client" EMS.
Requirements:
• 10+ years of experience in managing integrated circuit Design Technology including design rule
generation, device characterization and compact modeling and industry best practices.
• Extensive knowledge of compact modeling for Analog/RF and mixed-signal technologies
including high voltage MOS, BJT, BCD devices for circuit simulation.
• Extensive knowledge of integrated passive and active components characterization and modeling.
• Good verbal/written communication skills and proven ability to work in and lead cross functional
teams.
• Proven leadership and management skills in high technology industry.
• M.S. or PhD in Electrical Engineering, Physics, or related technical fields with > 10 years relevant
experience in logic, Analog/RF, and mixed-signal device & interconnect modeling as well as CAD
to support customer design.
• Working experience in TCAD device design is added advantage

Engineers Discover Fundamental Flaw In Transistor Noise?

I copy here a part of a post in EDN (follow the link to get the full story... be aware that this seems to be quite yellowish press!!!):

According to the engineers at the National Institute of Standards and Technology (NIST) who discovered the problem, it will soon stand in the way of creating more efficient, lower-powered devices like cell phones and pacemakers unless we solve it.

While exploring transistor behavior, the team found evidence that a widely accepted model explaining errors caused by electronic "noise" in the switches does not fit the facts. A transistor must be made from highly purified materials to function; defects in these materials, like rocks in a stream, can divert the flow of electricity and cause the device to malfunction. This, in turn, makes it appear to fluctuate erratically between "on" and "off" states. For decades, the engineering community has largely accepted a theoretical model that identifies these defects and helps guide designers' efforts to mitigate them.

Those days are ending, says NIST's Jason Campbell, who has studied the fluctuations between on-off states in progressively smaller transistors. The theory, known as the elastic tunneling model, predicts that as transistors shrink, the fluctuations should correspondingly increase in frequency.

However, Campbell's group at NIST has shown that even in nanometer-sized transistors, the fluctuation frequency remains the same. "This implies that the theory explaining the effect must be wrong," Campbell said. "The model was a good working theory when transistors were large, but our observations clearly indicate that it's incorrect at the smaller nanoscale regimes where industry is headed."

The findings have particular implications for the low-power transistors currently in demand in the latest high-tech consumer technology, such as laptop computers. Low-power transistors are coveted because using them on chips would allow devices to run longer on less power—think cell phones that can run for a week on a single charge or pacemakers that operate for a decade without changing the battery. But Campbell says that the fluctuations his group observed grow even more pronounced as the power decreased. "This is a real bottleneck in our development of transistors for low-power applications," he says. "We have to understand the problem before we can fix it—and troublingly, we don't know what's actually happening."

Campbell, who credits NIST colleague K.P. Cheung for first noticing the possibility of trouble with the theory, presented* some of the group's findings at an industry conference on May 19, 2009, in Austin, Texas. Researchers from the University of Maryland College Park and Rutgers University also contributed to the study.

Students from Microelectronics Students’ Group win Cadence® Contest

CADENCE® EMEA (Europe, Middle East and Africa regions) organized the first full custom design contest, entitled Virtuoso Olympics. In this unique and innovative event the best layout designers from the top academic institutions in Europe will compete for the title of Fastest full custom layout designer of the year.

Two students from the Microelectronics Students’ Group of the University of Porto (FEUP) won this Cadence® contest. Daniel Oliveira and Américo Dias accepted the challenge and accomplished the target, wining the first place.

An interesting discussion in LinkedIn

There is an interesting thread in LinkedIn, started by Antonio Irvin Aquino:

Is there a market for outsourced device modelling/simulation??

By the moment, I've seen no comments, but I should think that, at least, there is a market for outsourced device models courses...

Papers in Solid-State Electronics, May 2009

Three interesting new papers in the May 2009 issue of Solid-State Electronics:

A new analytical threshold voltage model for the doped polysilicon thin-film transistors
Weijing Wu, Ruohe Yao, Xueren Zheng

Compact model of short-channel MOSFETs considering quantum mechanical effects
G.S. Jayadeva, Amitava DasGupta

Modeling of kink effect in polycrystalline silicon thin-film transistors
Wanling Deng, Xueren Zheng

IEDM'09

The 2009 IEEE International Electron Devices Meeting (IEDM) will be held in the Hilton Baltimore Hotel in Baltimore (MD) from December 6 to 9 2009. This time IEDM will not be held in Washington after the San Francisco edition!

IEDM is the top conference in the field of electron devices. It is of course the most competitive one. Only truly outstanding papers are accepted. It is highly recommended that experimental results are shown, also some good simulation papers can be also accepted.

Two short courses will be held on Sunday, December 6, on on low power/low energy circuits and scaling challenges.

This year there will also be three plenary presentations. Furthermore, there will be a An Emerging Technology session on "Graphene Nanoelectronics".

Deadline for abstract submissions is June 26 2009 at 5.00 pm Pacific Standard Time.

Topics include all aspects related to electron devices, grouped in several areas:

-CMOS DEVICES & TECHNOLOGY (CDT)
-CHARACTERIZATION, RELIABILITY and YIELD (CRY)
-DISPLAYS, SENSORS, AND MEMS (DSM)
-MEMORY TECHNOLOGY (MT)
-MODELING AND SIMULATION (MS)
-PROCESS TECHNOLOGY (PT)
-QUANTUM, POWER, AND COMPOUND SEMICONDUCTOR DEVICES (QPC)
-SOLID STATE AND NANOELECTRONIC DEVICES (SSN)

This year the area of Modeling and Simulation (MS) explicitly includes "physical and compact models for devices and interconnects", and also "parameter extraction", and "early compact models for advanced technologies." It seems that compact modeling is considered a more important topic in IEDM than ever before!

If you have important results to show, I vively recommend to send an abstract to IEDM. It is the best place to present them, and to discuss them with the top people. Even if your abstract is rejected, or if you do not have any new results to show, I encourage researchers to attend IEDM, including compact modeling researchers.

BMAS'09

The 2009 IEEE International Behavioral Modeling and Simulation Conference (BMAS 2008) will be held in San Jose, CA, on September 17-18, in conjunction with the 2009 Custom Integrated Circuits Conference (CICC), in the Doubletree Hotel in San Jose, at the heart of Silicon Valley.

BMAS addresses behavioral modeling and simulation for analog electronic circuits and systems. One of the main areas of topics is "Semiconductor Device Compact Modeling", which includes: " Compact device modeling lanuages and compilers", "Standard and new compact device models implemented in Verilog-A and VHDL-AMS", and "Compact device models for emerging technologies and topical issues (nano-devices, distributed thermal effect, leakaging issues, manufacturability, radiation effects, etc)".

The deadline for paper submission is May 18 2009.

For compact and behavioral modeling researchers, BMAS is no doubt a very interesting conference to attend, and for circuit designers, it is a very good complement to CCIC.

Posted by Benjamin Iniguez at 08:04

Open Ph D Student position in semiconductor device modeling

We offer one scholarship for a Ph D student position in the Department of Electronic Engineering in the Universitat Rovira i Virgili (URV), in Tarragona, Spain.

The duration of the grant will be for four years. The monthly salary will be about 1000 Euro/month. The position will start in January 2009.

The candidate should have a Bachelor or Master degree in Electrical Engineering, Electronic Engineering, Telecommunication Engineering or Physics. A good background in Semiconductor Physics, Semiconductor Devices, or Integrated Circuit Design will be highly appreciated.

The work to be done by the candidate will be focused on the development of new techniques of characterization and modeling of novel advanced semiconductor devices, in particular III-V devices. It will be related to one European projects in which the hosting group participates.

Required documents for applicants


Applicants are required to send to the address specified below the following documents (in English or Spanish):

1) a full Curriculum Vitae (as complete as possible)

2) Copy of their diploma

3) copy of their passport

4) Academic certificate including their marks (it is important that the number of hours or credits of each subject appears). It is also very important that the document specifies what is the minimum mark for passing a given subject and what is the maximum mark that can be awarded.

Candidates can send their documents by e-mail, but in fact we will need original and copy documents (or authenticated copy) of them; therefore we also suggest to send the documents by postal mail.

Applications should be sent to:

Prof. Benjamin Iñiguez
Department of Electronic, Electrical and Automatic Control Engineering

Universitat Rovira i Virgili (URV)

Avinguda Països Catalans, 26
43007 Tarragona (Spain)
Email: benjamin.iniguez@gmail.com
Tel: +34977558521 Fax:+34977559610

Deadline: June 20 2009

You can contact Prof. Benjamin Iñiguez (Benjamin.Iniguez@gmail.com) for more information

Tarragona is a medium city (100000 inhabitants) with a Mediterranean climate and many recreation opportunities (nice beaches, theme parks, nature preserves, mountain hiking, touristic resorts and facilities). It is located 100 km Southwest of Barcelona, and it is very well connected by train, bus, highways and even low cost flights from its own airport. Additional information about the University and the department can be found at: www.urv.cat and sauron.etse.urv.es

Nano-Net 2009: International ICST Conference on Nano-Networks

Fourth International ICST Conference on Nano-Networks
18-20 October, 2009, Lucerne, Switzerland

The Nano-Net 2009 conference positions itself at the intersection of two worlds, namely, emerging nanotechnologies on one side, and Information & Communication Technologies on the other side. One of the standing questions that this conference addresses is: What are the new communication paradigms that derive from the transition from micro- to nano-scale devices? The convergence of nano-technologies with established and novel engineering disciplines such as communication and network theory, sensors and actuators, and biomedical engineering is expected to radically shift our notions about efficient system and network design. Nano- Net provides a unique multidisciplinary forum for the discussion of novel techniques in modeling, design, simulation, and fabrication of nano-scale systems.

The Nano-Net 2009 conference invites original technical papers that have not been published and are not currently under review for publication elsewhere. Contributions addressing subjects pertaining to nanotechnology and networking are solicited. Suggested topics include, but are not limited to the following:

• Emerging nano-devices and fabrication technologies
• Modeling and simulation of nano-devices and systems
• Nano-materials, nano-photonics
• Nano-electronics and architectures
• Reliability and fault-tolerance
• Nano-networks
• Nano-bio paradigms and applications
• Nanosensor Self-Organization
• Nano-mechatronics
• Emerging topics in nano-technologies

Important dates

• Workshop/Tutorial Proposals:May 31, 2009
• Paper Submissions: May 15, 2009
• Acceptance Notification:June 15, 2009
• Camera-Ready Version: July 15, 2009
• Nano-Net 2009 Conference: October 18-20, 2009

2009 IEEE International SOI Conference Deadline Extended

SUBMISSION DEADLINE EXTENDED!

The 2009 IEEE International SOI Conference Committee has extended the deadline
for submission of papers to be considered for presentation at the conference to
be held in Silicon Valley, California this October until 29-MAY.

This year's SOI conference will be highlighted by exciting invited talks. Some
of the topics to be covered are Synopsis, Rambus and Freescale on SOI design, on
technology from IBM and IMEC discussing the extendibility of SOI
technology beyond node 22nm to 16nm and 11; Peregrine will discuss RF
applications while Corning will present Silicon on Glass; and Soitec and Leti
will discuss the enabling possibilities of molecular bonding towards 3D
integration and nanotechnology. With the momentum that SOI based technologies is
gaining, the SOI conference is the ideal forum to exchange and network. The SOI
conference is an enriching forum where not only digital and power IC electronics
is discussed but also expands discussion to wafer engineering and circuit
transfer techniques opening up a spectrum of new applications like 3D,
photonics, nano-technologies and devices architectures beyond CMOS.

Submissions should be sent to soipaper@bacminc.com. Further information about
the conference, including an abstract template, can be found on the conference
web site at www.soiconference.org, or you may call the conference manager at
310/305-7885.

OSC'09

The 2008 Organic Semiconductor Conference (OSC-09) will take place in London (UK), from September 28 to 30 2009. The conference will be held at the London Heathrow Marriott Hotel. The hotel is conveniently located less than half a mile from Heathrow airport and has excellent road and public transport links to London and the rest of the UK.

OSC-09 includes sessions with presentations by invited speakers plus sessions with peer review papers, a poster session, and also an exhibition of leading organic semiconductor technology companies.

In addition, eight new pre-conference seminars covering a selection of popular topics will be held on Monday 28 September 2009. One seminar stream will be aimed at industry professionals to help them update and extend their knowledge, while a second stream will enable those new to the industry get up to speed. The invited speakers come from both academia and industry.

The Call for Papers will be published very soon. Topics include all aspects related to development, manufacturing and investment in organic semiconductor technologies and organic electronics. Besides, this year the conference will also explore the new opportunities offered by advances in carbon-based electronics.

OSC is not only attended by researchers in organic semiconductors, or organic electronics, but also by chief technology officers, senior technical staff, business leaders, investors, and manufacturers working in this promising field. Therefore, attending OSC there are great opportunities of business in all respects!

TNT'09

The Trends in Nanotechnology conference (TNT 2009) will be held in Barcelona (Catalonia, Spain) on September 7-11 2009.

TNT aims to present a broad range of top research in Nanoscience and Nanotechnology worldwide as well as related policies (European Commission, etc.) and initiatives (iNANO, IEEE, GDR-E, FinNano, etc.). TNT events have shown that they are particularly instrumental to disseminate information and establishing contacts among researchers in this field. Graduate students attending TNT have the chance to learn the importance of interdisciplinary skills, thereby becoming more effective in their future research.

TNT conferences provide an ideal venue for industrial, academic and governmental organizations to discuss common objectives and drive the commercialisation of nanotechnology discoveries.

One of the main goals of the Trends in Nanotechnology conference is to provide a platform where young researchers can present their latest work and also interact with high-level scientists. For this purpose, the Organising Committee provides every year travel grants for students. In addition, more than 20 awards are given to young PhD students for their contributions presented at TNT.

This year, TNT2009 organisation will provide around 100 graduate grants for PhD students:

- 10 Basque Country graduate grants (covering student fee) sponsored by NanoBasque / 325 Euros each - on the basis first come / first served
- 10 European graduate grants (travel bursaries) sponsored by GDR-I (topic of research: Nanotubes & Graphene) / 300 Euros each
- 40 nanoaracat graduate grants sponsored by nanoaracat:
-20 graduate grants for Aragon (travel bursaries) / 250 Euros each
-20 graduate grants for Cataluña (reduced fee) / student fee: 175 Euros (instead of 325)**after notification, a specific registration form will be available online to be able to register with the specific reduced fee.
- 20 Canadian PhD students: 1000 Canadian dollars travel-ship grants
- 20 graduate grants (travel bursaries) sponsored by TNT2009 organisation / 150 Euros each

The TNT2009 Organisation will also provide awards to the best posters presented by students

TNT2009 Deadlines:
Abstract Submission (Oral request): May 11,
2009 Student Grant (Travel bursary) Request: May 11, 2009
Submission (Poster request): July 20, 2009

Weather is usually very nice in Barcelona during the first half of September. Warm enough to go to the nice beaches that are at the city, or close to it, and swim on the sea. And not too hot to walk around.

IEEE SCV EDS upcoming meetings

1. EDS Meeting “Power and Variability”- May 12th (Tue)
2. Joint EDS-CPMT meeting “Through-Si vias” – May 13th (Wed)
3. EDS Meeting “NBTI in PMOS”- June 9th (Tue)

Please read details on the IEEE Santa Clara Valley EDS web site

ICECS'09, Dec. 13-16 2009, Hammamet, Tunisia

The 16th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2009, will be held in Tunisia on the 13th to 16th December 2009.

The IEEE International Conference on Electronics, Circuits, and Systems (ICECS) is the flagship conference of the IEEE Circuits and Systems (CAS) Society in region 8 (Europe, Middle East and Africa). It presents design methodologies, techniques and experimental results in emerging electronics, circuits and systems topics. ICECS 2009 will include tutorials, regular sessions (lecture and poster), Special sessions and exhibitions.

• CALL FOR PAPERS

MIT OpenCourseWare

MIT OpenCourseWare: Free Online Course Materials including lectures on the mosfet devices and CMOS technologies as well as other not only the Electrical Engineering and Computer Science topics. All together more than 1800 courses.

visit: MIT OpenCourseWare

[EDN] Andy Grove, Gordon Moore, other engineers honored by National Inventors Hall of Fame

Source: EDN

By Suzanne Deffree, Managing Editor, News -- Electronic News, 5/4/2009

Andy Grove and Gordon Moore were among a chosen few honored at the 2009 National Inventors Hall of Fame induction ceremony held on Saturday (May 2, 2009) at the Computer History Museum in Mountain View, Calif., USA.

The annual induction ceremony was held in Silicon Valley for the first time in celebration of 50 years of the IC and to honor 15 new inductees who have made significant contributions related to or enabled by semiconductors.

As credited by the National Inventors Hall of Fame, this year's 15 new inductees included:

Martin M (John) Atalla and Dawon Kahng, who worked to invent the first practical field-effect transistor;
Alfred Y Cho, who is credited as having achieved molecular beam epitaxy while at Bell Labs;
Ross Freeman, the co-founder of Xilinx who is credited as having invented the FPGA;
Dov Frohman-Bentchkowsky of Intel and founder of Intel Israel, who is credited as having created the EPROM (electrically programmable read-only memory) chip;
George Heilmeier, a liquid crystal display pioneer, former White House fellow, and former Texas Instruments CTO;
Jean Hoerni, co-founder of Fairchild Semiconductor and one of the Fairchild Eight, who is credited as having invented the planar manufacturing process;
Texas Instruments' Larry Hornbeck, who holds a series of patents that form the foundation for the digital micromirror device;
John Macdougall and Ken Manchester, who worked together to develop a commercially viable method of ion implantation;
Carver Mead, a professor emeritus at Caltech who helped to develop the standards and tools that permitted VLSI (very large-scale integration);
Gordon Moore, co-founder of both Fairchild and Intel and the author of Moore’s Law;
Gordon Teal, who is credited as having created the first functioning silicon transistor while at Texas Instruments;
Frank Wanlass, who is credited as having invented CMOS; and
Robert Widlar, who is credited with having designed the first commercially successful analog IC and who also co-founded Linear Technology Corp.

Andy Grove, who with Moore and Robert Noyce participated in the founding of Intel in 1968, was honored with the National Inventors Hall of Fame's Lifetime Achievement Award during the ceremony. Grove (pictured) was chairman of Intel's board from May 1997 to May 2005. From 1987 to 1998 he served as the company’s CEO and from 1979 to 1997 he served as president. Grove currently acts as a senior advisor to Intel.

The National Inventors Hall of Fame said it chose to honor Grove’s tenure because while at Intel's helm the company "dramatically contributed to the power, utility, and ubiquity of computing devices."

“The world we live in today is scarcely imaginable without the contributions of Andy Grove and all 15 of this year’s inductees,” said James Pooley, chairman of the National Inventors Hall of Fame, in a statement. “So many of the technologies we take for granted nowadays, including everyday consumer electronics like cell phones, computers, and DVD players, rely on semiconductor technologies that only exist thanks to their hard work and spirit of invention.”

Grove reportedly discussed patent laws and their impact on innovation at the event.

The National Inventors Hall of Fame is a not-for-profit organization dedicated to honoring and fostering creativity and invention. Headquartered in Akron, Ohio, it was founded in 1973 by the US Patent and Trademark Office and the National Council of Intellectual Property Law Associations.

ICOE'09

I post the official email I've got:
Just 7 weeks to go. The icoe shop is now live and open so that you can now register and the provisional programme has been organised (attached). The icoe registration fee is £270 while Ph.D. students are free. The oral/poster provisional programme is on the website as well as accommodation details. There is a Liverpool football club Tour and museum taking place on Wednesday afternoon (17^th June) at a cost of £10 per person while an organic roadmap talk/discussion is taking place at the same time. Further details and information can be found on the web site http://www.icoe09.com