Apr 27, 2022

[mos-ak] [Final Program] Spring MOS-AK Workshop April 29, 2022 (online)


Together with local host INAOE (MX), as well as all the Extended MOS-AK TPC Committee, would like to invite you to the Spring MOS-AK Workshop Compact/SPICE Modeling Workshop which will be organized as the virtual/online event on April 29, 2022

Upcoming online Spring MOS-AK Workshop aims to strengthen a network and discussion forum among experts in the field, create an open forum for sharing information related to compact/SPICE modeling and Verilog-A standardization, bring academic and industrial experts in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. The content will be helpful for anyone who needs to understand what is really behind the IC simulation in modern device models, in particular using Free 130nm Skywater PDK.

Final Spring MOS-AK Workshop Program is available online:

Online Registration Form 
https://forms.gle/2csBFMQXxMW7Ky5g8
Registered participants will receive an online meeting invitation 24h before the event. 
(any related enquiries can be sent to register@mos-ak.org)

Important Dates: 
  • Call for Papers: Feb. 2022
  • 3nd Announcement: April 5, 2022
  • Spring MOS-AK Workshop: April 29, 2022
    • Online Event 4:00pm - 6:00pm CET / GMT-1
Postworkshop Publications: Selected, the best MOS-AK technical presentation will be recommended for further publication in a special Solid State Electronics (SSE) issue on compact modeling.

-- W.Grabinski for Extended MOS-AK Committee
WG270422

Apr 26, 2022

[paper] 50 Two-Transistor MOSFET Circuits

Harald Pretl* and Matthias Eberlein**
Fifty Nifty Variations of Two-Transistor Circuits: A tribute to the versatility of MOSFETs
IEEE Solid-State Circuits Magazine 13(3):38-46, August 2021
DOI: 10.1109/MSSC.2021.3088968  
  
* Institute for Integrated Circuits, JKU, Linz, Austria
** Semiconductor electronics, TU, Darmstadt, Germany


Abstract: We present a compendium of two-MOS-transistor circuits, spanning the range from simple standard configurations to ingenious arrangements. Using these building blocks, circuit designers can assemble a vast array of complex analog functions. This (incomplete) collection shall serve as a reference and inspiration to junior circuit designers and hopefully contains at least one unexpected example for the professional engineer.

Part 1/2 #thisismagic #circuit #mosfet


Part 2/2 #thisismagic #circuit #mosfet

Acknowledgments: We thank the reviewers for their many mindful suggestions. We want to thank our colleagues at the Institute for Integrated Circuits, Johannes Kepler University Linz, for their support in preparing this manuscript and for their many enlightening discussions.

[paper] Universal Charge Model for Multigate MOS Structures

Kwang-Woon Lee and Sung-Min Hong
Derivation of a Universal Charge Model for Multigate MOS Structures
with Arbitrary Cross Sections
IEEE TED (2022, Early Access)
DOI:  10.1109/TED.2022.316486
   
* Gwangju Institute of Science and Technology (KR)

Abstract: A universal equation for the charge-voltage characteristics in the multigate metal oxide semiconductor (MOS) structure with an arbitrary cross section is presented. A generalized coordinate is proposed and the Poisson equation is integrated with a weighting factor related with the generalized coordinate and the electric field. A compact charge model is derived and analytic and numerical examples for various MOS structures are shown.
Fig: Thin slab in the semiconductor channel region of the multigate MOS structure. The A∗ surfaces are perpendicular to the z-direction, which is the transport direction and its generalized coordinate, ψ, for rectangular nanosheet MOS structures at 0.0 V (top) and 0.7 V (bottom).

Aknowlegements: This workwas supported by the National Research Foundation of Korea (NRF) Grant funded by the Korean Government under Grant NRF- 2019R1A2C1086656 and Grant NRF-2020M3H4A3081800.

[paper] DL Physics-Driven MOSFET Modeling

Ming-Yen Kao, H. Kam, and Chenming Hu, Life Fellow, IEEE
Deep-Learning-Assisted Physics-Driven MOSFET Current-Voltage Modeling
in IEEE Electron Device Letters
DOI: 10.1109/LED.2022.3168243

Abstract: In this work, we propose using deep learning to improve the accuracy of the partially-physics-based conventional MOSFET current-voltage model. The benefits of having some physics-driven features in the model are discussed. Using a portion of the Berkeley Short-channel IGFET Common-Multi-Gate (BSIM-CMG), the industry-standard FinFET and GAAFET compact model, as the physics model and a 3-layer neural network with 6 neurons per layer, the resultant model can well predict IV, output conductance, and transconductance of a TCAD-simulated gate-all-around transistor (GAAFET) with outstanding 3-sigma errors of 1.3%, 4.1%, and 2.9%, respectively. Implications for circuit simulation are also discussed.
Fig: (a) Model implementation for circuit simulations, without the relative gm and gds errors terms in the cost function, Model shows larger prediction error in (b) gm and (c) gds.

Acknowledgements: This work was supported by the Berkeley Device Modeling Center, 
UCB, CA (USA)




Apr 25, 2022

[paper] DC, LF noise and TID mechanisms in 16nm FinFETs

Stefano Bonaldoab, Teng Maab, Serena Mattiazzobc, Andrea Baschirottode, Christian Enzf, Daniel M.Fleetwoodg, Alessandro Paccagnellaab, Simone Gerardinab
DC response, low-frequency noise, and TID-induced mechanisms in 16-nm FinFETs for high-energy physics experiments
J. NIMA Section A; available online 18 April 2022, 166727
DOI: j.nima.2022.166727
     
a University of Padova (I)
b INFN Padova (I)
c University of Padova (I)
d INFN Milano (I)
e University of Milano Bicocca (I)
f ICLab, EPFL, Lausanne (CH)
g Vanderbilt University, Nashville (USA)

Abstract: Total-ionizing-dose (TID) mechanisms are evaluated in 16nm Si bulk FinFETs at doses up to 1 Grad (SiO2) for applications in high-energy physics experiments. The TID effects are evaluated through DC and low-frequency noise measurements by varying irradiation bias conditions, transistor channel lengths, and fin/finger layouts. The TID response of nFinFETs irradiated under positive gate bias at ultrahigh doses shows a rebound of threshold voltage with significant increase in the 1/f noise amplitude. The degradation is related to the generation of border and interface traps at the upper corners of STI oxides and at the gate oxide/channel interfaces. In contrast, pFinFETs have the worst degradation due to positive charge trapping in STI oxides, which severely degrades the device transconductance and total drain current, while negligible effects are visible in the threshold voltage and 1/f noise. The TID sensitivity depends strongly on the transistor layout. Short-channel devices have the best TID tolerance thanks to the influence of halo implantation, while pFinFETs designed with low number of fins have the worst degradation because of high densities of positive charge in the surrounding thick STI oxides. As a guideline for IC design, short-channel transistors with more than 4-fins may be preferred in order to facilitate circuit qualification.
Fig: Low-frequency noise measured at |Vds|=50mV and |Vgs|=0.85V at room temperature for pFinFET with Nfin=2 and L=16 nm, irradiated up to 1Grad (SiO2) in the ON condition

Acknowledgment: This work has been carried out within the FinFET16v2 experiment funded by the National Institute for Nuclear Physics - INFN, Italy.