Generalized EKV Compact MOSFET Model

On the Explicit Saturation Drain Current in the Generalized EKV Compact MOSFET Model

Francisco J. García-Sánchez, Life Senior Member, IEEE,

and Adelmo Ortiz-Conde, Senior Member, IEEE

IEEE TED Aug 9. 2021

DOI: 10.1109/TED.2021.3101186

*Solid State Electronics Laboratory, Universidad Simón Bolívar, Caracas 1080, Venezuela

Abstract: We present and discuss explicit closed-form expressions for the saturation drain current of short channel metal-oxide-semiconductorfield-effect transistors (MOSFETs) with gate oxide and interface-trapped charges, and including carrier velocity saturation, according to the generalized Enz-Krummenacher-Vittoz (EKV) MOSFET compact model. The normalized saturation drain current is derived as an explicit function of the normalized terminal voltages by solving the transcendental voltage versus charge equation using the Lambert W function. Because this special function is analytically differentiable, other important quantities, such as the transconductance and the transconductance-to-currentratio, can be readily expressed as explicit functions of the terminal voltages.

Fig: Comparison of simulated transfer characteristics with (red lines and symbols) and another without (black lines and symbols) radiation-induced oxide and interface-trapped charges. Calculation of V_GB versus ID_sat (lines) comes from denormalization and the explicit ID_sat versus V_GB (symbols) comes from denormalization of the proposed explicit expressions

IFS2021-MT Registration Now Open

IFS2021-MT Registration Now Open

Will the current shortages continue through 2022?  Get the answer to this and other key questions at IFS2021-MT, Future Horizons' Mid-Term Industry Webinar:
https://www.futurehorizons.com/page/135/

When?  Tue 14 Sep 2021
3 pm GMT / 7 am PST / 10am EST / 3pm GMT / 4pm CET / 11 pm JST

Where?  https://us02web.zoom.us/webinar/register/3616293135785/WN_9dsYHWvMTpaUAVf1cEIV3A

Why?  Now in its 33rd year, Future Horizons is committed to providing high quality, accurate, cost-effective market research and analysis to help industry leaders prepare themselves for the next new normal.  At January's IFS, we alone predicted 18 percent market growth for 2021, and were ridiculed at the time for being "ever-optimistic", but it was us who were right forcing all the other industry pundits to revise their forecasts in line with our views.

Our proven methodology, based on our analyses of the industry ecosystem and our interpretation of how these interact, is based on our 55 plus years of direct industry experience, longer than any other analyst and most industry execs. We are also not afraid to stick our necks out and go against the comsensus tide to ensure you get the right information, backed up by data and sound analytical process. As a result, our industry forecasts have consistently proved accurate and insightful, second to no-one. and this event will be no exception.

Our experience and deep insights makes this a must-attend event for any leader within the semiconductor, electronics and related industries.  Find out what's in store at IFS2021-MT, Future Horizons' Mid-Term Industry Webinar:
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What You Will Learn
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[mos-ak] [open registration] 18th MOS-AK ESSDERC/ESSCIRC Workshop Grenoble; Sept. 6, 2021

The MOS-AK/Grenoble Workshop Program is available online:
https://www.mos-ak.org/grenoble_2021/

Venue: Online MOS-AK Webinar; use the online form/link below to register:

https://forms.gle/neAwxTczP9PVE7uU6

Registered MOS-AK/Grenoble participants will receive an online access link on SEPT.3 before the main event;

any related enquiries can be sent to register@mos-ak.org

-- W.Grabinski; MOS-AK (EU)

WG240821

[book] Fully Depleted SOI

Sorin Cristoloveanu; Fully Depleted Silicon-On-Insulator:

Nanodevices, Mechanisms and Characterization
2021 Elsevier B.V. 

ISBN: 978-0-12-819643-4

Fully Depleted Silicon-On-Insulator provides an in-depth presentation of the fundamental and pragmatic concepts of this increasingly important technology.

There are two main technologies in the marketplace of advanced CMOS circuits: FinFETs and fully depleted silicon-on-insulators (FD-SOI). The latter is unchallenged in the field of low-power, high-frequency, and Internet-of-Things (IoT) circuits. The topic is very timely at research and development levels. Compared to existing books on SOI materials and devices, this book covers exhaustively the FD-SOI domain. 

Key Features:

• Written by a top expert in the silicon-on-insulator community and IEEE Andrew Grove 2017 award recipient
• Comprehensively addresses the technology aspects, operation mechanisms and electrical characterization techniques for FD-SOI devices
• Discusses FD-SOI’s most promising device structures for memory, sensing and emerging applications

Table of Contents:

Front Matter

Preface

Part I: Technology

Chapter 1 - FD-SOI technology pp. 3-37

Part II: Mechanisms in FD-SOI MOSFET

Chapter 2 - Coupling effects pp. 41-70

Chapter 3 - Scaling effects pp. 71-114

Chapter 4 - Floating-body effects pp. 115-138

Part III: Electrical characterization techniques for FD-SOI structures

Chapter 5 - The pseudo-MOSFET pp. 141-177

Chapter 6 - Diode-based characterization methods pp. 179-200

Chapter 7 - Characterization methods for FD-SOI MOSFET pp. 201-238

Part IV: Innovative FD-SOI devices

Chapter 8 - Electrostatic doping and related devices pp. 241-265

Chapter 9 - Band-modulation devices pp. 267-298

Chapter 10 - Emerging devices pp. 299-348

FD-SOI teasers pp. 349-352

Index

[mos-ak] Re: [Final Program] 18th MOS-AK ESSDERC/ESSCIRC Workshop Grenoble; Sept. 6, 2021

Arbeitskreis Modellierung von Systemen und Parameterextraktion
Modeling of Systems and Parameter Extraction Working Group
18th MOS-AK ESSDERC/ESSCIRC Workshop
Grenoble (online), Sept. 6, 2021

Together with local Host and MOS-AK Organizers as well as all the Extended MOS-AK TPC Committee, we invite you to the consecutive 18th MOS-AK ESSDERC/ESSCIRC Workshop. Scheduled Virtual/Online MOS-AK event aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors.

The MOS-AK Workshop Program is available online:
https://www.mos-ak.org/grenoble_2021/

Venue: Online MOS-AK Webinar; use the online form/link below to register:
https://forms.gle/neAwxTczP9PVE7uU6

Registered MOS-AK/Grenoble participants will receive an online access link on SEPT.3 before the main event;
any related enquiries can be sent to register@mos-ak.org

-- W.Grabinski; MOS-AK (EU)

WG180821

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[mos-ak] Re: [Final Program] 5th Sino MOS-AK Workshop Xi'an (hybrid/online) August 11-13, 2021

Arbeitskreis Modellierung von Systemen und Parameterextraktion 

Modeling of Systems and Parameter Extraction Working Group

5th Sino MOS-AK Workshop Xian

August 11-13, 2021

The Xidian University Host and local MOS-AK Organizers are providing following login information

Meeting link for 12th-13th. August  

https://meeting.tencent.com/s/HSfS9ZbTFZra

(no need to have password and can discuss/Q&A )

Meeting ID：357 1681 8021

Live channel: https://meeting.tencent.com/l/OWgMlNVDPe7E 

(can not discuss  just listen, password is 812813)

If anyone wants to attend MOS-AK Xian Training Course on 11th. August. 

https://meeting.tencent.com/s/xX8DrFfcVkWl

Meeting ID：716 195 769

Live channel: https://meeting.tencent.com/l/xPZezoHpYMwT 

(cannot discuss, just listen, password is 210811)

Please also note that all presentation timing listed in the workshop program  

https://www.mos-ak.org/xian_2021/

is in local Chinese time zone (GMT+8)

-- Min Zhang; XMOD Technologies (CN) 

-- W.Grabinski; MOS-AK (EU)

-- 

Enabling Compact Modeling R&D Exchange

www.mos-ak.org

--

WG080921

On Monday, July 5, 2021 at 5:30:55 PM UTC+2 Wladek Grabinski wrote:

Arbeitskreis Modellierung von Systemen und Parameterextraktion 

Modeling of Systems and Parameter Extraction Working Group

5th Sino MOS-AK Workshop Xian

August 11-13, 2021

Together with local Xidian University Host and MOS-AK Organizers as well as all the Extended MOS-AK TPC Committee, we have the pleasure to invite to the 5th Sino MOS-AK Workshop Xian workshop which will be Virtual/Online event. Scheduled, MOS-AK/Xian workshop, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors.

The MOS-AK Workshop Program is available online: 

https://www.mos-ak.org/xian_2021/

Venue: Hybrid event at Xidian University <xidian.edu.cn>

会议场所：西安电子科技大学北校区阶梯教学楼112报告厅, 

西安市雁塔区太白南路2号西安电子科技大学（北校区）

No.2, South Taibai Road, Xian Dianzi University, Xi'an, 710071

Online Registration is open

Workshop Secretary: Meng Zhang Mobile:13619295980

any related enquiries can be sent to regist...@mos-ak.org

Post-workshop publications, selected, the best papers will be selected and recommended for further publication in the renowned journal such as Weily's International Journal of Microwave and Optical Technology Letters special issue.

-- Min Zhang; XMOD Technologies (CN) 

-- W.Grabinski; MOS-AK (EU)

---

Enabling Compact Modeling R&D Exchange

www.mos-ak.org

---

WG050721

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[paper] Systematic approach for IG-FinFET amplifier design using gm/Id method

Alireza Hassanzadeh and Sajad Hadidi

Systematic approach for IG-FinFET amplifier design using gm/Id method

Analog Integrated Circuits and Signal Processing (2021)

https://doi.org/10.1007/s10470-021-01917-9

EE Department, Shahid Beheshti University, Tehran, Iran

Abstract: In this paper, a systematic approach has been used to apply gm/Id method for the design of Independent Gate (IG) FinFET amplifiers. The design of high-performance amplifiers using gm/Id method has been successfully applied to nanometer devices. IG-FinFETs have been widely used in digital circuit implementations. However, the application of IG-FinFETs in analog circuits is limited and brings many advantages including low power, low voltage operation of transistors. Independent gates of FinFET can receive different voltages that facilitate low voltage operation of the circuit. Simulation-based gm/Id method has been applied to IG-FinFET transistors and a systematic methodology has been developed for the design of IG-FinFET amplifiers. The Berkeley BSIM-IMG 55 nm technology parameters have been used for HSPICE simulations. The designed amplifier has a DC gain of about 45 dB while consuming 6.5 µW from a single 1 V power supply.

Fig: gm/Id vs. normalized Id(Vbg)

[paper] Compact Model for Electrostatics of III–V GAA Transistors

Mohit D. Ganeriwala, Francisco G. Ruiz*, Enrique G. Marin* and Nihar R. Mohapatra

A unified compact model for electrostatics of III–V GAA transistors with different geometries

Journal of Computational Electronics (2021)

Published: 07 August 2021

DOI: 10.1007/s10825-021-01751-2

 
Department of Electrical Engineering, Indian Institute of Technology Gandhinagar, Gandhinagar, Gujarat, 382355, India
*Department of Electronics, University of Granada, Granada, Spain

Abstract: In this work, a physics-based unified compact model for III-V GAA FET electrostatics is proposed. The model considers arbitrary cross-sectional geometry of GAA FETs viz. rectangular, circular and elliptical. A comprehensive model for cuboid GAA FETs is developed first using the constant charge density approximation. The model is then combined with the earlier developed model for cylindrical GAA FETs to have a unified representation. The efficacy of the model is validated by comparing it with simulation data from a 2D coupled Poisson-Schrödinger solver. The proposed model is found to be accurate for GAA FETs with different geometries, dimensions and channel materials and computationally efficient.

Fig: III–V GAA transistors with different geometries

Acknowledgements: This work is supported by the Visvesvaraya PhD scheme by MeitY, Gover nment of India Enrique G. Marin gratefully acknowledges Juan de la Cierva Incorporation IJCI-2017-32297 (MINECO/AEI).

#Tata Group Looking To Enter #Semiconductor #Manufacturing

#Tata Group Looking To Enter #Semiconductor #Manufacturing https://t.co/wRzBoxdPrf #semi https://t.co/B74v7K54NK

— Wladek Grabinski (@wladek60) Aug 9, 2021

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August 10, 2021 at 12:19AM
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[paper] #32bit microprocessor on #plastic

[paper] Z. Yu, “A #32bit microprocessor on #plastic,” Nature Electronics, Aug. 2021 https://t.co/K9hOZx05k6 #semi https://t.co/tO7TGBh5Gw

— Wladek Grabinski (@wladek60) Aug 9, 2021

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August 09, 2021 at 03:16PM
via IFTTT

Foxconn to Acquire Macronix's #6inch #wideband gap semiconductors #Wafer #Fab [EE Times Asia https://t.co/4fohHYy2za] #semi https://t.co/8St4KWqdnZ

Foxconn to Acquire Macronix's #6inch #wideband gap semiconductors #Wafer #Fab [EE Times Asia https://t.co/4fohHYy2za] #semi https://t.co/8St4KWqdnZ

— Wladek Grabinski (@wladek60) Aug 9, 2021

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August 09, 2021 at 11:41AM
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[paper] Compact Model for Thin-Film Heterojunction Anti-Ambipolar Transistors

Hocheon Yoo and Chang-Hyun Kim, Senior Member, IEEE 

Unified Compact Model for Thin-Film Heterojunction Anti-Ambipolar Transistors

IEEE Electron Device Letters (2021)

DOI 10.1109/LED.2021.3102219

* Department of Electronic Engineering, Gachon University, Seongnam 13120, South Korea

Abstract: This letter proposes an advanced compact model for anti-ambipolar transistors based on a lateral thin-film material heterojunction. The modeling idea focuses on an analytical description of component currents and bridging methods necessary for controllable transition between operation regimes. The model is validated by experimental data, and predictive simulations are carried out to demonstrate its applicabilities.

Fig: (a) Cross-sectional device structure of an AAT and its energy diagram at a negative VD (G: gate, S: source, and D: drain). (b) Conceptual illustration of the geometrical origin of the anti-ambipolar switching behavior.

Acknowledgements: This work was supported by the National Research Foundation of Korea (NRF) grants funded by the Korean government (MSIT) (NRF-2019 R1C1C1003356, NRF2020 R1A2C1101647).

[paper] Compact device modeling and simulation with Qucs/Qucs-S/Xyce modular libraries

Mike Brinson and Felix Salfelder 

Compact device modeling and simulation with Qucs/Qucs-S/Xyce modular libraries 

In 28th MIXDES (2021), pp. 35-40 

DOI: 10.23919/MIXDES52406.2021.9497545 

Abstract—The rapid development of new semiconductor materials and devices has highlighted the need for compact modeling and circuit simulation tools that can be easily adapted to accommodate emerging technologies. In most instances device modeling tools employ non-linear behavioural sources and Verilog-A modules for model prototype construction. This paper is concerned with the properties and application of modular user defined/plugin library toolkit that combines the best features of behavioural source and Verilog-A modeling practice while encouraging user extensions. The toolkit has been implemented as a Qucs/Qucs-S/Xyce modular library that is loadable on demand. To demonstrate its capabilities and flexibility a series of compact device models are introduced and their simulated performance presented and evaluated.

Fig: A Qucs-S/Xyce test bench for simulating and displaying BJT Ic/V ce

output characteristics with 1µA ≤ Ib ≤ 10µA in 1µA steps.

[paper] Model for Ultra-Scaled MoS2 MOSFET

Weiran Cai, Wenrui Lan, Zichao Ma*, Lining Zhang, Mansun Chan*

A Full-region Model for Ultra-Scaled MoS2 MOSFET Covering Direct Source-Drain Tunneling 

9th International Symposium on Next Generation Electronics (ISNE), 2021, pp. 1-3,

DOI: 10.1109/ISNE48910.2021.9493621

College of Electronic and Information Technology, Shenzhen University, Shenzhen, China

* Hong Kong University of Science and Technology, Hong Kong, China

Abstract: A full-region model for ultra-scaled monolayer MoS2 MOSFETs is reported in this work. The electrostatic potential in the scaled transistor structure is analyzed based on a first-principle verified potential model. A continuous full region current model is then developed to capture the short channel effects. Based on the potential model, the barrier height and width for direct source-drain tunneling are obtained. The direct tunneling module reproduces the essential physics observed from numerical device simulations. After integration with the thermionic emission model, the full-region current model is implemented into a SPICE simulator and the model convergence is verified by simulating typical circuits.

A drift-diffusion current model of the full region is straightforwardly derived with Taylor expansions of a Si model or from the Pao-Sah integral. It resembles the EKV current model and allows similar expressions of small signal models:

Fig: The impact of SCEs on devices of different channel length is showed in (a) Ids–Vg and (b) Ids–Vd characteristics predicted by the model covering SCEs. When channel length becomes smaller, SCEs becomes more serious. 

Acknowledgement: This work is supported in part by the Natural Science Foundation of China under Grant 61704144, the Shenzhen Science and Technology Project under JCYJ20180305125340386, the General Research Fund (GRF) from Research Grant Council (RGC) of Hong Kong under Grant 16206219

Please, no #Moore: '#Law' that defined how chips have been made for decades has run itself into a cul-de-sac

Please, no #Moore: '#Law' that defined how chips have been made for decades has run itself into a cul-de-sac https://t.co/O2hLg7hPWb #semi https://t.co/BbQV8R20tS

— Wladek Grabinski (@wladek60) Aug 6, 2021

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August 06, 2021 at 11:29AM
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[paper] Modeling and investigation of SET Inverter Circuit

C. Shyamala, V. Kalpana

Modeling and investigation of SET Inverter Circuit

International Journal of Innovative Research in Engineering 25 

Vol. 2, Issue 3 (May-June 2021), pp: 25-28 

ISSN No: 2582-8746; www.theijire.com

* Department of EEE, RV College of Engineering, VTU University, Karnataka. India.

Abstract: This paper presents an analytical model Inverter based on the theory of single electron transistor(SET). The proposed design is very flexible such that it can be used for single gate, multi-gate, symmetric, asymmetric devices and most importantly it can also consider the effect of background charge. It can also be used for large voltage range of drain-source voltage irrespective of the bias conditions. The proposed design has been simulated with SPICE and the characteristics produced by the proposed design have been verified against Monte Carlo simulator SIMON [1].

Fig: Schematic diagram of single electron inverter

Reference:

[1] SIMON - A single electron device and circuit simulator

https://www.lybrary.com/simon/examples.html

What is #TinyML, and why does it matter?

What is #TinyML, and why does it matter? https://t.co/6zq9Ar1ZU5 #semi https://t.co/Xqth7bzMYH

— Wladek Grabinski (@wladek60) Aug 5, 2021

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August 05, 2021 at 10:07AM
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Russian Forum "Microelectronics 2021

Russian Forum "Microelectronics 2021"

Preliminary Program

September 7-9, Moscow, JSC "ENPO SPELS"

The Scientific Conference Pre-session (based on Section 5)
Moderators: Bobkov S.G. IPPM RAS Nikiforov A.Yu. CEPE NRNU MEPhI

Section 1: Navigational communication VLSI and modules
Moderators: I. L. Korneev JSC NIIMA Progress Steshenko VB JSC "RKS"

Section 2: High performance computing systems
Moderators: Khrenov G.Yu. JSC "Baikal Electronics" Bychkov I.N. JSC "MCST"

Section 3: Information control and radio engineering systems
Moderators: Pereverzev A.L. NRU MIET Yakunin A.N. NRU MIET P.M. Eremeev JSC "Research Institute" Submicron "

Section 4: Technologies and components of micro- and nanoelectronics
Moderators: Shelepin N.A. JSC "NIIME" Putrya M.G. NRU MIET Egorov A.Yu. LLC "Connector Optics"

Section 5: Micro- and optoelectronic products for general and special purposes
Moderators: Bobkov S.G. IPPM RAS Nikiforov A.Yu. CEPE NRNU MEPhI

Section 6: Design and simulation systems for electronic components and systems
Moderators: Rusakov S.G. Corresponding member of RAS Zavalin Yu.V. JSC "NIIMA" Progress "

Section 7: Microwave integrated circuits and modules
Moderators: Minnebaev V.M. JSC "NPP" Pulsar " P.V. Panasenko JSC "NIIME" Mukhin I.I. JSC "NIIMA" Progress "

Section 8: Microsystems. Sensors and Actuators
Moderators: Timoshenkov S.P. NRU MIET Dyuzhev N.A. STC NMST

Section 9: Special technological equipment
Moderators: Biryukov M.G. JSC NIITM Alekseev A.N. CJSC "NTO"

Section 10: Neuromorphic computing. Artificial intelligence
Moderators: Kryzhanovsky B.V. FGU FSC NIISI RAS Tel'minov O.A. JSC "NIIME" Gornev E.S. JSC "NIIME"

Section 11: Quantum Technologies - Quantum Sensors
Moderators: Gorbatsevich A.A. FIAN, NRU MIET Bogdanov Yu.I. FTIAN, NRU MIET S.P. Kulik Moscow State University named after M.V. Lomonosov

IJHSES Special Issue Volume 29, Issue 01n04, 2020

IJHSES Special Issue on Nanotechnology for Electronics, Biosensors, 

Additive Manufacturing and Emerging Systems Applications 

Guest Editors: F. Jain, C. Broadbridge, M. Gherasimova and H. Tang

Volume 29, Issue 01n04 (March, June, September, December 2020) 

This Special issue on Nanotechnology for Electronics, Biosensors, Additive Manufacturing and Emerging Systems Applications comprises peer reviewed articles selected from the 29th annual symposium of the Connecticut Microelectronics and Optoelectronics Consortium (CMOC), virtually held on October 2, 2020 and hosted by Information Technology Staff, University of Connecticut (Storrs Campus).

Organized by a team of seven academic institutions and about eighteen companies across the United States, this symposium sign-posted the progress and development of state-of-arts research in high-speed electronics over the last 30 years.

Articles include keynote presentations by three experts in their field:

• Dr. H. Lee, Electronic and IR Sensing in Forensics, U. New Haven, and Henry Lee Center for Forensic Research
• Dr. E. Fossum, Quanta Image Sensor, Dartmouth College
• Dr. J. Chow, Quantum Computing, IBM Thomas J. Watson, Research Center

The papers presented span from novel materials and devices, biosensors and bio- nano- systems, artificial intelligence, robotics and emerging technologies, to applications in each of these fields, Systems for implementing data with security tokens; single chemical sensor for multi-analyte mixture detection; RF energy harvesters; additively manufactured RF devices for 5G, IoT, RFID and smart city applications are also included in this special issue on high performance materials for implementing high-speed electronic systems.

In the area of material synthesis, modeling of dislocations behavior in various II-VI and III-V heterostructures and their gettering at sidewall bringing novel approaches are also featured

Coming hot on the heels, are recent developments on high performance devices include equivalent circuits models at room and 4.2K; quantum dot nonvolatile memories, 3D- confined quantum dot channel (QDC) and spatial wavefunction switched (SWS) FETs for high-speed multi-bit logic and novel system applications.

In summary, the papers selected for this special issue cover various aspects of h performance materials and emerging devices for implementing high-speed electronic systems. We would like to take this opportunity to express our thanks to the authors, participants, and reviewers for their contributions and active participation, networking, and knowledge sharing on a variety of research areas.