[thesis] RF UTBB FDSOI MOSFET

Vanbrabant, Martin

RF characterization of the back-gate contact on Fully Depleted SOI MOSFETs

http:// hdl.handle.net/2078.1/thesis:26763

Ecole polytechnique de Louvain, Université catholique de Louvain, 2020. 

Academic year 2019–2020: Master in Electrical Engineering

Prom.: Prof. Jean-Pierre Raskin

Readers: Denis Flandre, Valeriya Kilchytska, Lucas Nyssens, Martin Rack

Abstract: Thanks to the thin buried-oxide, the UTBB FDSOI technology with a highly doped region under the BOX is one of the main candidates for future RF applications. One of the most interesting feature of this technology is the possibility to tune the threshold voltage, compensate variability issues and improve the overall device performance. In this work, the impact of the back-gate bias is mainly studied on the threshold voltage and RF FoMs of the front and back-gates.

Figure: Reconstructed (dashed) vs initial (full) Re{Yij} insaturationat VDS=0.8V, VGS=0.8V and VB=0V for a 4-port device.

#Precursor is a mobile, open source electronics platform

#Precursor is a mobile, open source electronics platform. Similar to Raspberry Pi or an Arduino it can be transformed into an IoT gadget with just a couple breakout boards, some solder, and a bit of code for variety of DIY mobile applications https://t.co/XQkrw0coiK #semi pic.twitter.com/QtZup2uRgk

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#EPFL President M. Vetterli Takes On #Gender #Equality, COVID-19, and #Science Policy

#EPFL President Martin Vetterli Takes On #Gender #Equality, COVID-19, and #Science Policy https://t.co/Id0pjw1MHN #semi pic.twitter.com/MifKfRHe7B

— Wladek Grabinski (@wladek60) September 28, 2020

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What is #FOSS? What is #OpenSource?

Linux Jargon Buster: What is #FOSS (Free and Open Source Software)? What is #OpenSource? https://t.co/BdVZucwpO4 #semi pic.twitter.com/BwLlHWbJIB

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ASCENT+ project

ASCENT+ project "Access to European Infrastructure for Nanoelectronics​" coordinated by #Tyndall National Institute (SINANO member) https://t.co/Nvc2UIUt86 #Semi pic.twitter.com/6bc4VlV1WN

— Wladek Grabinski (@wladek60) September 25, 2020

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#Opensource chip tech #RISC-V

#Opensource chip tech #RISC-V could be a major #beneficiary of Arm's $40 billion sale to Nvidia https://t.co/WwYt79AmrU pic.twitter.com/SMwZuPD9xx

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[paper] Ultra-High Voltage SiC IGBT

Wide-Range Prediction of Ultra-High Voltage SiC IGBT Static Performance

Using Calibrated TCAD Model

Daniel Johannesson^1,2, Keijo Jacobs¹, Staffan Norrga¹, Anders Hallén³, 

Muhammad Nawaz² and Hans-Peter Nee^1,2

Materials Science Forum Submitted: 2019-09-19

ISSN: 1662-9752, Vol. 1004, pp 911-916  

DOI:10.4028/www.scientific.net/MSF.1004.911

¹Division of Electric Power and Energy Systems, KTH , Sweden
²ABB Corporate Research, Västerås, Sweden
³Division of Electronics, KTH, Sweden

Abstract: In this paper, a technology computer-aided design (TCAD) model of a silicon carbide (SiC) insulated-gate bipolar transistor (IGBT) has been calibrated against previously reported experimental data. The calibrated TCAD model has been used to predict the static performance of theoretical SiC IGBTs with ultra-high blocking voltage capabilities in the range of 20-50 kV. The simulation results of transfer characteristics, IC-VGE, forward characteristics, IC-VCE, and blocking voltage characteristics are studied. The threshold voltage is approximately 5 V, and the forward voltage drop is ranging from VF = 4.2-10.0 V at IC = 20 A, using a charge carrier lifetime of τA = 20 μs. Furthermore, the forward voltage drop impact for different process dependent parameters (i.e., carrier lifetimes, mobility/scattering and trap related defects) and junction temperature are investigated in a parametric sensitivity analysis. The wide-range simulation results may be used as an input to facilitate high power converter design and evaluation. In this case, the TCAD simulated static characteristics of SiC IGBTs is compared to silicon (Si) IGBTs in a modular multilevel converter in a general highpower application. The results indicate several benefits and lower conduction energy losses using ultra-high voltage SiC IGBTs compared to Si IGBTs.

Fig: 4H-SiC IGBT structure implemented in 2D TCAD simulator

Acknowledgment This work was funded through SweGRIDS, by the Swedish Energy Agency and ABB.

[paper] Multi-Bridge-Channel Field Effect Transistor

Leakage Performance Improvement in Multi-Bridge-Channel Field Effect Transistor

(MBCFET) by Adding Core Insulator Layer 

Saehoon Joung^1,2, Student Member, IEEE and SoYoung Kim², Senior Member, IEEE 

SISPAD 2019 

DOI:10.1109/sispad.2019.8870498 

¹Samsung Electronics Co. Foundry Division, Yield Enhancement, Process Integration Engineering Group, Ltd Kiheung, Republic of Korea
²College of Information and Communication Engineering,Sungkyunkwan University, Suwon,Gyeounggi-do, Republic of Korea

Abstract: Altering from existing planar devices to FinFETs has revolutionized device performance, but demands of leakage and gate controllability are increasing relentlessly. Gate all around field effect transistor (GAAFET) is expected to be the next-generation device that meets these needs. This paper suggests a way to improve the gate electrostatic characteristics by adding an oxidation process to the conventional multi-bridgechannel field effect transistor (MBCFET) process. The main advantage of the proposed method is that a device with ultimate electrostatic properties can be implemented without changing the complex and expensive photo-patterning. In the proposed device, the immunity of short channel effects is enhanced in a single transistor. And the performance of ring oscillator (RO) and SRAM was confirmed to be improved by TCAD mixed-mode simulation.

FIG: MBCFET Process Flow Comparison 

 

Acknowledgement: This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (No. NRF-2017R1A2B2003240). The TCAD tools were supported by the IC Design Education Center (IDEC).

[mos-ak] Fwd: MOS-AK / IEEE-EDS-MQ / SSB-MOS Workshops at THM - Deadline extended

Dear colleagues and friends, 

please note that the registration deadline for the

Joint Spring MOS-AK Workshop and 

Symposium on Schottky Barrier MOS (SB-MOS) devices with 

IEEE EDS Mini-Colloquium on „Non-conventional Devices and Technologies" 

has been extended. 

The event hosted by THM will take place in Zoom as live presentations Sept. 29 to Oct. 1. 

Please register until Sept. 25 by use of IEEE vTools: 

https://meetings.vtools.ieee.org/m/205571
The registration is for free. 

Preliminary program: 

https://ssbmos.blogspot.com/p/programm-2020.html and 

http://www.mos-ak.org/giessen_2020

Registered attendees will receive the Zoom link for the event a few days before via email from vTools.

Important new dates: 
1st Event Announcement: Aug. 2020 
2nd Event Announcement: Sept. 2020 
Final Workshop Program: Sept. 2020
Registration deadline (extended): Sept. 25, 2020
"Spring" MOS-AK Workshop: Sept. 29/30, 2020 
IEEE MQ: Sept. 30/Oct. 1, 2020
Symposium SB-MOS devices: Oct. 1, 2020

Best regards

Alexander Kloes

_____________________________________________________________

Prof. Dr.-Ing. Alexander Kloes

 

Technische Hochschule Mittelhessen - University of Applied Sciences

Department Electrical Engineering and Information Technology

Spokesperson of Competence Center Nanotechnology and Photonics

Director of Doctoral Theses at Universitat Rovira i Virgili, Tarragona

Wiesenstrasse 14

D-35390 Giessen

Germany

E-mail: alexander.kloes@ei.thm.de

Web: go.thm.de/dmrg-en and www.thm.de

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#TSMC's development of #2nm process technology, which is already out of its pathfinding mode, is ahead of schedule, according to industry sources https://t.co/7jiFBRomRy #semi https://t.co/ieDnhSHxZh

#TSMC's development of #2nm process technology, which is already out of its pathfinding mode, is ahead of schedule, according to industry sources https://t.co/7jiFBRomRy #semi pic.twitter.com/ieDnhSHxZh

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[paper] 2D Charge Density Wave Phases

Machine-Intelligence-Driven High-Throughput Prediction of 2D Charge Density Wave Phases

Arnab Kabiraj and Santanu Mahapatra*

J. Phys. Chem. Lett. 2020, 11, 15, 6291–6298

Publication Date:July 22, 2020

DOI: 10.1021/acs.jpclett.0c01846

*Nano-Scale Device Research Laboratory, IISc Bangalore, India

Abstract: Charge density wave (CDW) materials are an important subclass of two-dimensional materials exhibiting significant resistivity switching with the application of external energy. However, the scarcity of such materials impedes their practical applications in nanoelectronics. Here we combine a first-principles-based structure-searching technique and unsupervised machine learning to develop a fully automated high-throughput computational framework, which identifies CDW phases from a unit cell with inherited Kohn anomaly. The proposed methodology not only rediscovers the known CDW phases but also predicts a host of easily exfoliable CDW materials (30 materials and 114 phases) along with associated electronic structures. Among many promising candidates, we pay special attention to ZrTiSe4 and conduct a comprehensive analysis to gain insight into the Fermi surface nesting, which causes significant semiconducting gap opening in its CDW phase. Our findings could provide useful guidelines for experimentalists.

Fig: Top view of TaSe₂-H 3×3_ɸ-1.

Si2 VAMPyRE: compact model parser and checker

Si2 #Compact #Model #Coalition Offers VAMPyRE, the software is a standalone compact model parser and checker written in Python, to Members and Developers https://t.co/vPQWlcQ99l pic.twitter.com/gbUq5nBFOA

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[tutorial] next generation 3D nano device simulator

Single-electron transistor - laterally defined quantum dot - 3D Tutorial

Stefan Birner

https://www.nextnano.com

Single-electron transistor - laterally defined quantum dot In this tutorial, we simulate an AlGaAs/GaAs heterostructure grown along the z direction. This structure leads to a two-dimensional electron gas (2DEG). By appying a gate voltage on top of the structure in the (x,y) plane, one is able to deplete the 2DEG and a laterally defined QD is formed. By adjusting the gate voltage, one is able to tune the number of electrons that are inside the QD.

This figure shows the conduction band edge Ec(x,y) and the electron density n(x,y) for the 2DEG plane, i.e. at z = 8 nm below the GaAs/AlGaAs heterojuntion. The geometry of the top gates is indicated by the blue regions. The following figure shows the calculated conduction band edge and the electron density of the heterostructure. The results are similar to Fig. 4 in paper [1].

The following figure shows two 2D slices through the lateral (x,y) plane at a distance of 8 nm below the AlGaAs/GaAs interface. In the middle, the electron density is shown. The electron density has been calculated classically. At the bottom, the conduction band edge is shown. The results are similar to Fig. 5 in paper [1]. At the top, the four gates are shown.

REF:

[1] A. Scholze, A. Schenk, W. Fichtner; Single-Electron Device Simulation; IEEE TED 47, 1811 (2000)

[paper] OTFTs in Mechanical Sensors

Organic Thin Film Transistors in Mechanical Sensors 

Zachary A. Lamport, Marco Roberto Cavallari^2,3, Kevin A. Kam, 

Christine K. McGinn, Caroline Yu, and Ioannis Kymissis

DOI: 10.1002/adfm.202004700

¹Department of Electrical Engineering, Columbia University, USA
²Departamento de Engenharia de Sistemas Eletrônicos, EPU de São Paulo, Brazil
³Department of Renewable Energies. UNILA, Brazil

Abstract: The marriage of organic thin-film transistors (OTFTs) and flexible mechanical sensors has enabled previously restricted applications to become a reality. Counterintuitively, the addition of an OTFT at each sensing element can reduce the overall complexity so that large-area, low-noise sensors can be fabricated. The best-performing instance of this is the active matrix, used in display applications for many of the same reasons, and nearly any type of flexible mechanical sensor can be incorporated into these structures. In this Progress Report, some of the flexible sensor devices that have taken advantage of these mechanical properties are highlighted, examining the advantages that OTFTs offer in the hybrid integration of local amplification and switching. In particular, the current research on resistive pressure sensors, capacitive pressure sensors, resistive or piezoresistive strain sensors, and piezoelectric sensors is identified and enumerated.

Fig: Suspended-gate FET: a) Schematic illustration of device geometry; b) electrical equivalent circuit; c) pressure response of ID at constant VDS = VGS = −60 V

Acknowledgements C.M. received funding from the National Science Foundation Graduate Research Fellowship Program (DGE—1644869). Z.L. thanks Corning and the NSF under STTR 1914013 for financial support.

[paper] Memristors in SPICE

Modeling networks of probabilistic memristors in SPICE

Vincent J. Dowling¹, Valeriy A. Slipko², Yuriy V. Pershin¹

arXiv:2009.05189v1 [cs.ET] 11 Sep 2020

DOI: 10.13164/re.2020.0001

¹Department of Physics and Astronomy, University of South Carolina, Columbia, SC 29208 USA
²Institute of Physics, Opole University, Opole 45-052, Poland

Abstract. Efficient simulation of probabilistic memristors and their networks requires novel modeling approaches. One major departure from the conventional memristor modeling is based on a master equation for the occupation probabilities of network states. In the present article, we show how to implement such master equations in SPICE. In the case studies, we simulate the dynamics of ac-driven probabilistic binary and multi-state memristors, and dc-driven networks of probabilistic binary and multi-state memristors. Our SPICE results are in perfect agreement with known analytical solutions. Examples of LTspice codes are included.

Fig: Ac-driven probabilistic binary memristor: (a) simulated circuit, (b) schematics of SPICE model, and (c) example of current-voltage curves found with SPICE simulations. The listing of SPICE model is given in Apendix.

Appendix: SPICE code examples

B1 0 p0 I=-gm(tau01,V01,V(Va))*V(p0)*u(V(Va))+gm(tau10,V10,-V(Va))*V(p1)*u(-V(Va))

B2 0 p1 I=gm(tau01,V01,V(Va))*V(p0)**u(V(Va))-gm(tau10,V10,-V(Va))*V(p1)**u(-V(Va))

C1 p0 0 1 IC=1

C2 p1 0 1 IC=.0

R2 Va 0 1k

R1 Va 0 10k

R3 VI 0 1k

B3 0 VI I=I(R1)*V(p0)+I(R2)*V(p1)

V1 Va 0 SINE(0 1 200 0 0 0 0)

.FUNC gm(x,y,z)1/(x*exp(-z/y))

.param tau01=3E5 V01=.05

.param tau10=3E5 V10=.05

.tran 0 .1 0.05 10E-7

.backanno

.end

[paper] Co-designing electronics with microfluidics

Remco van Erp, Reza Soleimanzadeh, Luca Nela, Georgios Kampitsis & Elison Matioli; Co-designing electronics with microfluidics for more sustainable cooling. Nature 585, 211–216 (2020). DOI: 10.1038/s41586-020-2666-1 https://t.co/WQ3ddWLuqp #paper pic.twitter.com/gqt3iVegwp

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[paper] Compact Model for MoS2 FETs

A physics-based compact model for MoS2 field-effect transistors

considering the band-tail effect and contact resistance

Yuan Liu¹, Jiawei Zeng², Zeqi Zhu¹, Xiao Dong² and WanLing Deng³

Japan Society of Applied Physics; Accepted Manuscript online 11 September 2020

¹Guangdong University of Technology, Guangzhou, Guangdong, CHINA

²Jinan University, Guangzhou, Guangdong, CHINA
³Electronic Engineering, Jinan University, Guangzhou, GuangDong, 510630, CHINA

Abstract: In this paper, we present a compact surface-potential-based drain current model in molybdenum disulfide (MoS2) field-effect transistors (FETs). Considering variable range hopping (VRH) transport via band-tail states in MoS2 transistors, an explicit solution for surface potential has been derived and it provides a good description over different regions of operation by comparisons with numerical data. Based on charge-sheet model (CSM) which applies to drift-diffusion transport, the current expression including contact resistance and velocity saturation effect is developed. Furthermore, the presented model is validated and shows a good agreement with experiment data for MoS2 FETs. Keywords: molybdenum disulfide (MoS2), surface potential, current expression.

Fwd: September 2020 Newsletter: Planet-Scale Processing of Silicates

September 2020 Newsletter: Planet-Scale Processing of Silicates In the eastern Sierra Nevada mountains, near Mammoth Lakes, California, is a geological phenomenon: a cliffside lined with thousands of 10-20 meter tall pillars of basalt. The organized rock columns are so incongruous with the surrounding high altitude pine forest that they seem supernatural. Shepherds who frequented the area in the 1800's named it the "Devil's Woodpile." Today, it's a popular park called the Devils Postpile National Monument. To a MEMS engineer, this odd rock cliff bears a striking resemblance to the columnar grains in thin film PZT or ZnO. What a mind bender to see familiar shapes from SEM images towering overhead. Like PZT or ZnO, a special set of environmental conditions created the Devils Postpile. It was not, however, the result of grain growth; instead, the Postpile formed from a pool of lava which then cracked into a network of polygons as it cooled. (More like misprocessed thick photoresist!) A scale factor of 20 million: PZT with columnar grains (top) compared to basalt columns (bottom). Sources: http://dx.doi.org/10.1021/acsami.6b16470, http://www.nps.gov/depo On top of the Devils Postpile, one particular area has a smooth surface which reveals the cross-sections of the polygonal columns, 50-100 cm in width. This most unusual stone patio was formed by the water, pressure, and motion of a passing Ice Age glacier, a massive-scale version of chemical mechanical polishing (CMP). Basalt rock is primarily composed of SiO2 (45-52% by weight) and other metal oxides, such as TiO2, Al2O3 and MgO; all familiar MEMS materials, just in a much larger format. Ancient CMP: cross-section of basalt columns, polished flat by a glacier. Note the fine lines that were created by grit trapped in the moving glacier. Four kilometers from the Postpile is the stunning 30 meter tall Rainbow  Falls, etched through two layers of volcanic rock. The top masking layer of rock is harder than the thick underlayer of softer rhyodacite. Water pouring over the edge erodes the soft rock at a faster rate, leaving a re-entrant cliff face and thereby creating a beautiful waterfall. An idle thought while hiking on a hot summer day: Is geology just a planet-scale version of MEMS processes? Please note: AMFitzgerald's business operations are continuing normally despite COVID *and* California wildfires. Where to Meet Us Virtually SEMI/MSIG Executive Congress Virtual More information October 6-8 and 13-15, at 8:00 am – 10:30 am PDT  About Us A.M. Fitzgerald & Associates, LLC ("AMFitzgerald") provides complete solutions for MEMS product development. Our full service engineering capabilities include: custom MEMS design to specification, semi-custom RocketMEMS® pressure sensors, process integration, prototype and short-run fabrication, multiphysics finite element modeling, foundry selection and transfer with support through production, and technology strategy consulting.  We turn your ideas into silicon - find out how For more information call: (650) 347-MEMS / (650) 347-6367 CONNECT WITH US! ‌

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[paper] Low-voltage, Non-volatile, Compound-semiconductor Memory Cell

Room-temperature Operation of Low-voltage, Non-volatile, Compound-semiconductor Memory Cell

Ofogh Tizno, Andrew R. J. Marshall, Natalia Fernández-Delgado, Miriam Herrera, Sergio I. Molina
and Manus Hayne

Scientific Reports volume 9, Article number: 8950 (2019) 

DOI: 10.1038/s41598-019-45370-1

Abstract: Whilst the different forms of conventional (charge-based) memories are well suited to their individual roles in computers and other electronic devices, flaws in their properties mean that intensive research into alternative, or emerging, memories continues. In particular, the goal of simultaneously achieving the contradictory requirements of non-volatility and fast, low-voltage (low-energy) switching has proved challenging. Here, we report an oxide-free, floating-gate memory cell based on III-V semiconductor heterostructures with a junctionless channel and non-destructive read of the stored data. Non-volatile data retention of at least 10000s in combination with switching at ≤2.6 V is achieved by use of the extraordinary 2.1 eV conduction band offsets of InAs/AlSb and a triple-barrier resonant tunnelling structure. The combination of low-voltage operation and small capacitance implies intrinsic switching energy per unit area that is 100 and 1000 times smaller than dynamic random access memory and Flash respectively. The device may thus be considered as a new emerging memory with considerable potential.

FIG: Device structure a) Schematic of the processed device with control gate (CG), source (S) and drain (D) contacts (gold). The red spheres represent stored charge in the floating gate (FG). b) Cross-sectional scanning transmission electron microscopy image showing the high quality of the epitaxial material, the individual layers and their heterointerfaces.

Simulation Methods: The nextnano software package was utilised for mathematically modelling the energy band diagram of the memory device structure reported here, taking into account strain and piezoelectricity. Within this work, a self-consistent Schrödinger solver was used along with the Poisson and drift–diffusion equations to calculate the electron densities at equilibrium and under bias.

The Industry’s First SoC FPGA Development Kit Based on the #RISC-V Instruction Set Architecture is Now Available | Microchip Technology https://t.co/1CCwP6GR3h #semi https://t.co/TKw7mFqOcC

The Industry’s First SoC FPGA Development Kit Based on the #RISC-V Instruction Set Architecture is Now Available | Microchip Technology https://t.co/1CCwP6GR3h #semi pic.twitter.com/TKw7mFqOcC

— Wladek Grabinski (@wladek60) September 16, 2020

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FreePDK15: Process Design kit for 15-nm FinFETs

Development of a Predictive Process Design kit for 15-nm FinFETs: FreePDK15 

Kirti Bhanushali, Chinmay Tembe, and W. Rhett Davis 

arXiv:2009.04600v1 [cs.AR] 9 Sep 2020

Abstract: FinFETs are predicted to advance semiconductor scaling for sub-20nm devices. In order to support their introduction into research and universities it is crucial to develop an open source predictive process design kit. This paper discusses in detail the design process for such a kit for 15nm FinFET devices, called the FreePDK15. The kit consists of a layer stack with thirteen-metal layers based on hierarchical-scaling used in ASIC architecture, Middle-of-Line local interconnect layers and a set of Front-End-of-Line layers. The physical and geometrical properties of these layers are defined and these properties determine the density and parasitics of the design. The design rules are laid down considering additional guidelines for process variability, challenges involved in FinFET fabrication and a unique set of design rules are developed for critical dimensions. Layout extraction including modified rules for determining the geometrical characteristics of FinFET layouts are implemented and discussed to obtain successful Layout Versus Schematic checks for a set of layouts. Moreover, additional parasitic components of a standard FinFET device are analyzed and the parasitic extraction of sample layouts is performed. These extraction results are then compared and assessed against the validation models.

FIG: Middle-of-Line layers used as interconnects

Acknowledgment: The authors would like to thank Paul Franzon at NC State University. The authors would like to thank Mentor Graphics, since this project would not have been possible without their generous gift of supporting funds and Calibre licenses. The authors would also like to thank Tarek Ramadan, Ahmed Hammed Fathy, Omar El-Sewefy, Ahmed El-Kordy, Hend Wagieh and the team at Mentor Graphics for development of the first set of design rules and their constant support.In addition, the authors would like to thank and acknowledge Alexandre Toniolo at Nangate for clarifying the vision of MOL layers. We would also like to thank Cadence designsystems for use of the virtuoso software and Synopsys Inc.for use of Pycell studio. The authors would also like to thanks Vikas Sharma for P-Cells, Vidyanandgouda Patil for design rule fixes and Namrata Sampat for help cleaning up the distribution.

Online Lecture Workshop On Frontiers in Science & Engineering - Opportunities for Graduates (Sept 14-19, 2020)

Respected All

On behalf of the organizing committee of the Science Academies Online Lecture Workshop On Frontiers in Science & Engineering - Opportunities for Graduates (Sept 14-19, 2020),

I am sharing separate Zoom Links for each day. 

You are requested to register yourself for one or more sessions by registering separately.

Kindly forward this email to your friends, students and colleagues from all branches of science and engineering. 

• Kindly join at least 15 minutes before the session.
• Letter of attendance for each day will be provided at the end of the session.

September 15, 2020 (Zoom Link: https://zoom.us/webinar/register/WN_JF5EVXqsTBCcHLIuL2e7dA)

• 04:00 pm – 05:00 pm - The Lead Halide Perovskites: Photoluminescence and Charge Carrier Dynamics - Professor Anunay  Samanta, FASc, FNASc, FNA, Sr. Professor and J.C. Bose National Fellow (DST), School of Chemistry, University of Hyderabad
• 05:00 pm – 06:00 pm  - Interdisciplinary Education for Science and Innovation - Professor Sourav Pal, FASc, FNASc, FNA, Director, Indian Institute of Science Education & Research, West Bengal  

September 16, 2020  (Zoom Link: https://zoom.us/webinar/register/WN_hbdn7CqUQMqWUeyaW7qJTA)

• 06:00 pm – 07:00 pm Electronic Cash, Cryptocurrencies and Smart Contracts - Professor Rudrapatna Kallikote Shyamasundar, FASc, FNA, FNASc, FNAE, FIEEE, FTWAS, Distinguished V Professor, Computer Science & Engineering Department, IIT Powai

September 17, 2020  (Zoom Link: https://zoom.us/webinar/register/WN_KG1XHg1gReWXDbW4Asg39w)

• 06:00 pm – 07:00 pm -  Indian Healthcare, Digital Transformation, and COVID-19 - Dr Anurag Agrawal, FNA, Director, CSIR-Institute of Genomics and Integrative Biology, Mall Road, Delhi University
• 07:00 pm – 08:00 pm  - Responsibilities and opportunities for academics in the context of current pandemic - Dr. Rakesh K Mishra, FASc, FNASc, FNA, Director, CSIR-Centre for Cellular & Molecular Biology, Hyderabad

September 18, 2020 (Zoom Link: https://zoom.us/webinar/register/WN_Hqv3xXODT8-jkMuZmT3eXg)

• 06:00 pm – 07:00 pm - Continued fraction expansions of complex numbers - Prof. Shrikrishna Gopalrao Dani, FASc, FNA, FNASc, Distinguished Professor, Centre for Excellence in Basic Sciences, University of Mumbai, Maharashtra  
• 07:00 pm – 08:00 pm - C.R.Rao and Mahalanobis' Distance - Prof. Probal Chaudhuri, FASc, FNA, FNASc, Theoretical Statistics and Mathematics Unit, Indian Statistical Institute, Kolkata  
  

September 19, 2020 (Zoom Link: https://zoom.us/webinar/register/WN_xDWQkmHdSl69mfci1yLnLA)

• 06:00 pm – 07:00 pm  - Future Geosciences and Opportunities - Prof. Ashok Kumar Singhvi, FASc, FNA, FNASc, FTWAS, Honorary Scientist, Atmospheric, Molecular & Optical Physics Divn., PRL, Gujarat
• 07:00 pm – 08:00 pm  - Glasses and other amorphous solids - Professor  Srikanth Sastry, FASc, FNASc, FNA, Theoretical Sciences Unit, JNCASR, Bangalore, Karnataka

with regards

Dr. Manoj Saxena | डॉ मनोज  सक्सेना 

Associate Professor | सह - आचार्य

Department of Electronics | इलेक्ट्रॉनिक्स विभाग

Deen Dayal Upadhyaya College | दीन दयाल उपाध्याय कॉलेज

University of Delhi | दिल्ली विश्वविद्यालय

Dwarka Sector-3, New Delhi-110078 | द्वारका क्षेत्र -३, नई दिल्ली -११००७८

India | भारत

Official Homepage: https://dducollegedu.ac.in/ViewProfile.aspx?fId=saxenamanoj77@gmail.com

ORCID Webpage : http://orcid.org/0000-0002-9368-4194

Scopus Webpage : http://www.scopus.com/authid/detail.url?authorId=35480023200

ResearcherID-Thomson Reuters : http://www.researcherid.com/rid/K-3863-2015 

Publons Profile: https://publons.com/researcher/1341187/manoj-saxena

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[mos-ak] Fwd: ESSCIRC ESSDERC 2020 Virtual Educational Events | IMPORTANT MESSAGE

View this email in your browser ESSCIRC ESSDERC 2020 VIRTUAL EDUCATIONALS LIVE EXECUTIVE SESSIONS: September 14, 15  ON DEMAND September 7 - October 16 Hello, You are receiving this message because you registered for the ESSCIRC ESSDERC 2020 Virtual Educational Events. How is it going so far?  Feel free to use the Q&A box to send us questions: all questions will be gathered end of the week and will be transmitted to the event organizers prior to the Live events next week. Take also advantage of the POLLS in the following Educational Events:  3. WORKSHOP | Non-Volatile Memories: Opportunities and Challenges from Devices to Systems 10. DISSEMINATION WORKSHOP |  Toward sustainable IOT from rare materials to big data 11. DISSEMINATION WORKSHOP | High Density 3D CMOS Mixed-Signal Opportunities 12. MOS-AK WORKSHOP | Compact/SPICE Modeling and its Verilog-A Standardization Questions and polls will be discussed during the LIVE EXECUTIVE SESSIONS. Mark your calendar! How to access the Live Executive Sessions? Once logged in, you see a small window on the left called "ADDITIONAL RESOURCES": the hyperlink to live session is there and, of course, it will be active only during live sessions  Last but not least, if you are experiencing some connections problems while using your office PC, check with your IT staff if firewalls prevent you from connecting to the on-line virtual events.  See you there! ORGANIZING COMMITTEE Thomas Ernst (CEA-LETI, FR), General co-chair Dominique Thomas (STMicroelectronics, FR), General co-chair François Andrieu (CEA-LETI, FR), ESSDERC TPC Chair Maud Vinet (CEA-LETI, FR), ESSDERC TPC co-Chair Andreia Cathelin (STMicrolectronics, FR), ESSCIRC TPC Chair Sylvain Clerc (STMicrolectronics, FR), ESSCIRC TPC co-Chair 2020 Virtual Educationals Chairs Sylvain Clerc (STMicrolectronics, FR) Ionut Radu (SOITEC, FR) LOCAL EXECUTIVE SECRETARIAT Sandra Barbier (CEA-LETI, FR) | sandra.barbier@cea.fr ORGANIZING SECRETARIAT Sistema Congressi s.r.l. | essxxrc@sistemacongressi.com  JOIN NOW OUR  ESSCIRC – ESSDERC LinkedIn group! Share Forward ORGANIZERS TECHNICAL SPONSORSHIP FINANCIAL SPONSORSHIP DIAMOND SPONSOR WATCH ME Copyright © 2020 Sistema Congressi s.r.l., All rights reserved. You are receiving this email because you registered for ESSCIRC ESSDERC 2020 Virtual Events Our mailing address is: Sistema Congressi s.r.l. Via Trieste 26 Padova, PD 35121 Italy Add us to your address book

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