[Call for Participation] FOSDEM 2016 Electronic Design Automation Devroom

 Call for Participation 

FOSDEM 2016 Electronic Design Automation Devroom 

This is the call for participation in the FOSDEM 2016 devroom on Free/Open Source Software (FOSS) Electronic Design Automation (EDA) tools, to be held on Saturday 30 January 2016 in Brussels, Belgium. We are looking for contributions under the form of talks covering the following main topics:

• Printed Circuit Board (PCB) design tools (e.g. KiCad and gEDA)
• Analogue and digital simulators (e.g. ngspice, Qucs, Gnucap, Xyce, GHDL, Icarus and Verilator)
• Any other EDA tools such as high-level tools for digital hardware design (e.g. Migen)
• Inter-project opportunities for collaboration

We hope to provide an opportunity for attendees to bring themselves up to date on the latest FOSS EDA developments, share knowledge and identify opportunities to collaborate on development tasks. Have a look at last year's event for a taste of what the EDA devroom is about.

The submission process
Please submit your proposals at https://penta.fosdem.org/submission/FOSDEM16 

before 4 December 2015.

If you already have a Pentabarf account (for example as a result of having submitted a proposal in the past), make sure you use it to log in and submit your proposal. Do not create a new account if you already have one. Please provide a bit of information about yourself under Person -> Description -> Abstract. When you submit your proposal (creating an "Event" in Pentabarf), make sure you choose the "EDA devroom" in the track drop-down menu. Otherwise your proposal might go unnoticed. Fill in at least a title and abstract for the proposed talk and a suggested duration. Bear in mind that a lot of the value in these meetings comes from the discussions, so please be reasonable regarding the duration of the talk.

Important dates

• 4 December 2015: deadline for submission of proposals
• 18 December 2015: announcement of final schedule
• 30 January 2016: devroom day

[Read More]

[Purdue e-Pubs] A physics-based compact model for thermoelectric devices

A physics-based compact model for thermoelectric devices

Kyle Conrad, Purdue University; Mark S. Lundstrom, Purdue University (Advisor)

Abstract: Thermoelectric devices have a wide variety of potential applications including as coolers, temperature regulators, power generators, and energy harvesters. During the past decade or so, new thermoelectric materials have been an active area of research. As a result, several new high figure of merit (zT) materials have been identified, but practical devices using these new materials have not yet been reported. A physics-based compact model could be used to simulate a thermoelectric devices within a full system using SPICE-compatible circuit simulators. If such a model accepts measured or simulated material parameters, it would be useful in exploring the system level applications of new materials. In this thesis, the ground work for such a compact model is developed and tested. I begin with a discussion of thermoelectric transport theory within the Landauer formalism. The Landauer formalism is used as the basis of the tool LanTraP, which uses full band descriptions to calculate the distribution of modes and thermoelectric transport parameters, which can serve as the input to a compact model. Next, an equivalent circuit model is presented, explained, and tested using a simple Bi2Te 3 thermoelectric leg. The equivalent circuit is shown to perform well under a variety of DC, transient, and AC small signal operating conditions. With the equivalent circuit it is easy to determine the maximum cold side temperature drop, the maximum cold side heat absorbed, the temperature profile within the leg, the temperature response to a pulsed current, and impedance over a range of frequencies. Finally, Sentaurus®, a computer program that solves the thermoelectric transport equations numerically, is used to compare and benchmark some of the results of the equivalent circuit when considering Si as the thermoelectric material. The equivalent circuit and Sentaurus® simulations produce similar results in DC and transient cases, but in the AC small signal case the two simulations produce slight differences. The results of this work establishes a baseline compact model for thermoelectric devices whose accuracy and capabilities can be extended.

[read more...]

[mos-ak] [2nd Announcement and Call for Papers] 8th International MOS-AK Workshop Washington DC December 9, 2015

 8th International MOS-AK Workshop 
 Washington DC December 9, 2015 
 2nd Announcement and Call for Papers 

Together with the MOS-AK Workshop Scientific Program Coordinators Larry Nagel and Andrei Vladimirescu, as well as Extended MOS-AK TPC Committee, we have pleasure to invite to the MOS-AK Workshop which will be held in Washington DC in the IEDM / CMC meetings timeframe Planned MOS-AK workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Venue:    

Embassy of Switzerland
2900 Cathedral Ave, NW,  
Washington, DC 20008 
USA 

Important Dates:

• Call for Papers - Sept. 2015
  
• 2nd Announcement - Oct. 2015
  
• Final Workshop Program - Nov. 2015
• MOS-AK Workshop - Dec, 9, 2015
• http://www.mos-ak.org/washington_dc_2015/
  
• 08:30 - 09:00 - On-site Registration 
  
• 09:00 - 10:30 - Morning MOS-AK Session
• 11:00 - 12:00 - CM Standardization Pannel
  
• 12:00 - 13:00 - Lunch
• 13:00 - 16:00 - Afternoon MOS-AK Session 

Topics to be covered include the following:

• Advances in semiconductor technologies and processing
• Compact Modeling (CM) of the electron devices
• Verilog-A language for CM standardization
• New CM techniques and extraction software
• Open Source TCAD/EDA modeling and simulation
• CM of passive, active, sensors and actuators
• Emerging Devices, CMOS and SOI-based memory cells
• Microwave, RF device modeling, high voltage device modeling
• Nanoscale CMOS devices and circuits
• Technology R&D, DFY, DFT and IC Designs
• Foundry/Fabless Interface Strategies

Tentative MOS-AK speakers list

• Mathieu Luisier (ETHZ) TCAD for nanoscaled devices
• Mansun Chan (HKUST) iMOS online simulation platform
  
• Akira Ito (Broadcom) Leading-edge RF MOSVAR Modeling 
• Samuel Mertens (Cadence)
• Rob Jones (Raytheon), GaN FET model standardization
• Klaus-Willi Pieper (Infineon)
• Ehrenfried Seebacher (ams) DIODE_CMC standard diode model
• Colin Shaw (Silvaco) CMC OMI - based on TSMC TM
• Joddy Wang (Synopsys) FinFET SPICE modeling
  
• Mike Brinson (Qucs) EDD Verilog-A Prototyping Platform
• Mark Lundstrom (Purdue)
• Jaijeet Roychowdhury (UCB) Model and Algorithm Prototyping Platform (MAPP)

Online Abstract Submission:
Authors should submit an abstract using on-line MOS-AK submission form:

http://www.mos-ak.org/washington_dc_2015/abstracts.php

(any related inquiries can be sent to abstracts@mos-ak.org)
 
Free Online Workshop Registration:

http://www.mos-ak.org/washington_dc_2015/registration.php
(any related inquiries can be sent to registration@mos-ak.org)
 
Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee

WG102015

--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To post to this group, send email to mos-ak@googlegroups.com.
Visit this group at http://groups.google.com/group/mos-ak.
For more options, visit https://groups.google.com/d/optout.

IEDM: Modeling and Simulation – Compact Modeling

 IEEE International Electron Devices Meeting (IEDM) is the world’s preeminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices, novel quantum and nano-scale devices and phenomenology, optoelectronics, devices for power and energy harvesting, high-speed devices, as well as process technology and device modeling and simulation. This year IEDM technical program also includes a series of the compact modeling papers:

[9.6] GaNFET Compact Model for Linking Device Physics, High Voltage Circuit Design and Technology Optimization, U. Radhakrishna, S. Lim, P. Choi, T. Palacios, and D.A Antoniadis, Massachusetts Institute of Technology
[28.1] Transport Mechanism in sub 100C Processed High Mobility Polycrystalline ZnO Transparent Thin Film Transistors, P.B. Pillai, and M.M. De Souza, University of Sheffield
[28.2] Physical-based Analytical Model of flexible a-IGZO TFTs Accounting for Both Charge Injection and Transport, M. Ghittorelli, F. Torricelli, J.L. Van Der Steen*, C. Garripoli**, A. Tripathi*, G. Gelinck*, E. Cantatore**, Z. Kovacs-Vajna, University of Brescia, *Holst Centre, TNO, **Eindhoven University of Technology
[28.3] Predictive Compact Modeling of Random Variations in FinFET Technology for 16/14nm Node and Beyond, X. Jiang, X. Wang*, R. Wang, B. Cheng**, A. Asenov*, and R. Huang, Peking University, *University of Glasgow, **Gold Standard Simulations (GSS) Ltd.
[28.4] A New Surface Potential Based Physical Compact Model for GFET in RF Applications, L. Wang, S. Peng, Z. Zong, L. Li, W. Wang, G. Xu, N. Lu, Z. Ji, and M. Liu, Chinese Academy of Sciences
[28.5] Physics-based Compact Modeling Framework for State-of-the-Art and Emerging STT-MRAM Technology, N. Xu, J. Wang, Y. Lu, H.-H. Park, B. Fu, R. Chen, W. Choi, D. Apalkov, S. Lee*, S. Ahn*, Y. Kim*, Y. Nishizawa**, K.-H. Lee, Y. Park, Samsung Semiconductor Inc, *Samsung Electronics, **Samsung R&D Institute Japan
[28.6] Physics-based Compact Modeling of Charge Transport in Nanoscale Electronic Devices (Invited), S. Rakheja, and D. Antoniadis*, New York University, *Massachusetts Institute of Technology

The compact/SPICE modeling and its Verilog-A standardization will be also discussed at two following engineering events organized by MOS-AK Group and the CMC which are collocated with the IEDM in Washington DC in December, later this year.

[online MOS-AK and CMC registration]

• MOS-AK Workshop in Washington DC (Dec.9) 
• http://www.mos-ak.org/washington_dc_2015/
• CMC Meeting at Sheraton Suites Old Town Alexandria (Dec.10-11)
• https://www.si2.org/openeda.si2.org/4Q_2015_CMC_Meeting.php

Nature - Column: World View - Science must prepare for impact

  Nature | 30 September 2015 | Column: World View | Science must prepare for impact

To maintain public support, researchers need to be able to adapt to the rapidly changing needs of society and politicians, warns Guy Poppy U.Southampton. [read more]