Call for Papers PRIME 2015

 The PRIME 2015 Call for Papers is available at: 

 http://web.eng.gla.ac.uk/prime2015/static/images/PRIME2015CFPv2.pdf 

The purpose of the PRIME Conference is to grow Ph.D students' experience in the early stage of their career by creating a connection between academic world and companies.

A Workshop is organized for all conference participants on June 29th. Moreover, a Company Fair is organized for all conference participants, to create a connection between major companies in Electronics/Microelectronics and Ph. D students.

PRIME 2015 topics of interest include, but are not limited, to:

• Micro/nanoelectronics
• Semiconductors
• Analog and Digital Signal Processing
• Computer Aided Design
• Analog, Digital, Mixed-Signal and RF IC Design
• Integrated Power ICs
• RF, Microwave and Millimeterwave Circuits
• VLSI and SoC Applications
• Visual Signal Processing
• Sensor Systems and MEMS
• Energy Scavenging
• Technical trends and challenges
• Electronic Skin

[read more...]

Meet with Silvaco at IEDM 2014

Silvaco will showcase at IEDM products for applications such as displays, power devices, optical devices, advanced CMOS process development, radiation & soft error reliability, analog and memory design.

• Victory Process, Device and Stress for 1D, 2D and 3D TCAD simulation for applications such as TFT displays, IGBT power devices, lasers, image sensors, advanced CMOS devices such as FDSOI and FinFETs, radiation and soft error reliability simulation
• Clever for 3D parasitic RC extraction with the highest accuracy capacitance extraction for application such as TFT design, FinFET SRAM analysis
• Utmost IV for creating SPICE models for any device type including TFT, UOTFT, BSIM-CMG for FinFETs, HSIM-HV2 for high voltage devices
• Affordable and complete custom design flow including schematic entry, layout, simulation, analysis and verification ideally suited to analog, power management applications and for process nodes such as 65nm/40nm that are key targets for Internet of Thing (IoT) designs
• SmartSpice for simulation of circuits such as analog/mixed-signal, HSIO, RF, SRAM, standard cells, TFT panels, power ICs and for which recent performance enhancement benchmark data will be shared
• SmartSpice for library, memory and critical path characterization with built-in optimizers and circuit rubber-banding capability, having achieved 16nm FinFET model certification and includes PODE and ETMI reliability model support
• SmartSpice Soft Error Reliability capability that is used to analyze the impact of Single Event Effects (SEE) on circuit performance, an increasingly important challenge at 20nm and below technology nodes 

More information at their website.