Magma FineSim SPICE Supports STARC HiSIM Model with Proven 20x Faster Circuit Simulation and Nearly Exact Correlation to Silicon. Or so they say in their web. See the full press release for more details. However, I love one of the sentences: "STARC's mission is to contribute to the growth of the Japanese semiconductor industry by developing leading-edge system-on-a-chip (SoC) design technologies.". Well, I would think that their primary mission is creating value for they investors, but one never knows. Now seriously, it is good to see that people is beginning to provide support (or implementations) of HiSIM. I only hope that foundries will follow the path, instead of being stuck with good (well, perhaps not so much), old (yes it is) BSIM3.1. I know this is a version of many years ago, but I can promise you that I've been playing with a 120nm technology using it.
By the way, by the moment it seems that more people is implementing HiSIM than PSP... curious, isn't it?
Mar 28, 2007
Mar 27, 2007
Call for Grant applications at SRC
SRC-GRC is calling for grant applications in Cross-disciplinary Semiconductor Research. The role of this program is to stimulate non-traditional thinking about the issues facing the semiconductor industry. It is intended to seed new research and programs for the SRC-GRC and SRC-FCRP. Consistent with the incubator role of the initiative, these will be 1 year non-overhead bearing grants at a funding level of $40K.
The scope of this solicitation is Nanoscale CMOS-Based Architectures. The challenge: Sustaining CMOS value progression through functional scaling and system design. The deadline: may, 1st. In principle, this is not for compact models, but I think that a good proposal including compact modeling could be redacted. Why? Because new devices are required to address the challenges of the next years and there is no way to do it without good compact models. So, at least a part of a sensible proposal should include some compact modeling (if nothing more, some way to go from compact device models to compact functional models... otherwise no real achivements will be obtained but only some old techniques re-edited)
By the way, IBM India is looking for Compact Model Engineers. Have a look at their web.
The scope of this solicitation is Nanoscale CMOS-Based Architectures. The challenge: Sustaining CMOS value progression through functional scaling and system design. The deadline: may, 1st. In principle, this is not for compact models, but I think that a good proposal including compact modeling could be redacted. Why? Because new devices are required to address the challenges of the next years and there is no way to do it without good compact models. So, at least a part of a sensible proposal should include some compact modeling (if nothing more, some way to go from compact device models to compact functional models... otherwise no real achivements will be obtained but only some old techniques re-edited)
By the way, IBM India is looking for Compact Model Engineers. Have a look at their web.
Mar 23, 2007
Another blog
I've found another blog about semiconductors. It is basically about technology news, but it is quite interesting to look at. You can reach it here (by the way, the name is Semiconductor Highlights). It is not frequentely updated, but it has a long history. In any case, if any of you, dear hipothetical readers, feels like suggesting another blog, don't hesitate to post it here...
Mar 20, 2007
DCIS'07
The last call for papers has been issued for the DCIS'07. This conference has evolved from its origins, more than two decades ago, into an important international meeting for researches in the highly active fields of micro and nano electronics circuits and integrated systems. It provides an excellent forum to present and investigate the emerging challenges in modelling, design, implementation and test of circuits and systems. Experts from both industry and academia have the chance to discuss the demands and solutions for current applications. Strong scientific, technical and personal relationships have been developed in the frame of this event. Moreover, there will be at least one session dedicated to modelling. So, it is a very good opportunity to visit Sevilla!
Mar 16, 2007
MIGAS'07 Summer School will focus on Multi-Physics and Multi-Scale Simulation
The International Summer School on Advanced Microelectronics (MIGAS) has become probably the top summer school held in Europe in the field of semiconductor devices. MIGAS is organized by the Institut National Polytechnique de Grenoble (INPG) and the Center for Innovation in Micro & NanoTechnology (MINATEC). The venue is always a beautiful town or resort in the Alps close to Grenoble. This year MIGAS'07 (June 24-29) will take place in Autrans, a well-known alpine resort, offering many kind of outdoor opportunities: hiking, mountain climbing, mountain-biking,...
Every year MIGAS addresses a different topic. This year, MIGAS'07 (10th Session) will be devoted to Multi-Physics and Multi-Scale Simulation for NanoElectronics.
It is well known that traditional modeling tools are not suitable to simulate the behaviour of nanoelectronic devices. The invited lecturers will explain new methods to model nanoscale devices:
-Non-equilibrium Green's functions methods (M.P. Anantram, Waterloo, Canada)
-Ab-initio methods (X. Blase, Lyon, France)
-Wigner functions methods (P. Dollfus, Paris, France)
-Monte Carlo methods (D. Esseni, Udine, Italy)
-Kp methods (F. Michelini, Marseille, France)
-Tight-binding methods (Y.M. Niquet, Grenoble, France)
-Deterministic solution of the Boltzmann Transport Equation (C. Jungemann, Munich, Germany)
In addition, there will be lectures on nanoscale device process simulation (M. Jaraiz, Valladolid, Spain), quantum transport theory (D.K. Ferry, Arizona, USA) , noise in nanoelectronics (G. Iannaccone, Pisa, Italy), and also characterisation techniques (S. Cristoloveanu, Grenoble, France) . Finally, I will conduct a lecture on the compact modeling of nanoscale MOSFETs.
No doubt MIGAS'07 will be a very interesting opportunity for students and researchers to become familiar with the new modeling methods proposed for the novel nanoelectronic devices.
Every year MIGAS addresses a different topic. This year, MIGAS'07 (10th Session) will be devoted to Multi-Physics and Multi-Scale Simulation for NanoElectronics.
It is well known that traditional modeling tools are not suitable to simulate the behaviour of nanoelectronic devices. The invited lecturers will explain new methods to model nanoscale devices:
-Non-equilibrium Green's functions methods (M.P. Anantram, Waterloo, Canada)
-Ab-initio methods (X. Blase, Lyon, France)
-Wigner functions methods (P. Dollfus, Paris, France)
-Monte Carlo methods (D. Esseni, Udine, Italy)
-Kp methods (F. Michelini, Marseille, France)
-Tight-binding methods (Y.M. Niquet, Grenoble, France)
-Deterministic solution of the Boltzmann Transport Equation (C. Jungemann, Munich, Germany)
In addition, there will be lectures on nanoscale device process simulation (M. Jaraiz, Valladolid, Spain), quantum transport theory (D.K. Ferry, Arizona, USA) , noise in nanoelectronics (G. Iannaccone, Pisa, Italy), and also characterisation techniques (S. Cristoloveanu, Grenoble, France) . Finally, I will conduct a lecture on the compact modeling of nanoscale MOSFETs.
No doubt MIGAS'07 will be a very interesting opportunity for students and researchers to become familiar with the new modeling methods proposed for the novel nanoelectronic devices.
Mar 14, 2007
Technology news
I've found a curious article at the EE Times Europe (a nice journal, by the way). The title is "Graphene transistor to rival silicon, say researchers". Some researchers at the University of Manchester and at the Max Planck Institute claim that they have developed a transistor that is 1 atom thin. Read the full story at the link above, but I've loved the last sentence: "Professor Geim indicated graphene based circuits would not come of age before 2025 and till then silicon based devices would predominate.". This is long-term research... Now, seriously, what they are developing, if it can be used industrialy, will be a revolution, bringing single electron devices to life. However, we shall have to wait 18 years more.
Mar 13, 2007
Links
I've found some interesting links about Compact Modeling. The first one is the homepage of Dr. Zhou Xing, at the Nanyang Technological University (Singapore). A quite interesting page, with links to many of his papers and works.
The second link is more educational, and contains the material of a course in the "Grupo de Electrónica del Estado Sólido de la Universidad Simón Bolívar" (Caracas, VENEZUELA). The only drawback of this excellent page is that it is in a mixture of Spanish and English. However, the completeness of the page fully justifies a visit.
The second link is more educational, and contains the material of a course in the "Grupo de Electrónica del Estado Sólido de la Universidad Simón Bolívar" (Caracas, VENEZUELA). The only drawback of this excellent page is that it is in a mixture of Spanish and English. However, the completeness of the page fully justifies a visit.
Mar 9, 2007
Carbon Nanotubes
I've been informed that the Journal of Semiconductor Science and Technology freely distributes (up to april, 18th) its special issue on charge and transport on Carbon Nanotubes. It is a very interesting topic, and the papers are both reviews and original research. I think it is an opportunity not to be missed.
Mar 8, 2007
Compact charge and capacitance models of nanowire MOSFETs
The compact modeling of nanowire MOSFETs (also called surrounding gate MOSFETs or Gate All Around MOSFETs) is a hot topic. The first compact drain current models were published in 2004:
Researchers are now addressing the compact modeling of charges and capacitances. In January 2007, in IEEE Transactions on Electron Devices, the first compact model for charges and capacitances of surrounding gate MOSFETs was published: Analytical Charge and Capacitance Models of Undoped Cylindrical Surrounding-Gate MOSFETs, by Moldovan O., Jiménez D., Roig J. and Iñiguez B.
In March 2007, a new charge model for surrounding gate MOSFETs has been published in IEEE Transactions on Electron Devices: Analytic Charge Model for Surrounding-Gate MOSFETs, by Yu B., Lu W.-Y., Lu H. and Taur, Y.
Both models are based on the electrostatic potential soultion obtained by D. Jimenez et al. (Continuous analytic I-V model for surrounding-gate MOSFETs, IEEE Electron Device Letters, August 2005)
from the 1-D Poisson's equation in the radial direction (neglecting the effect of the lateral field). B. yu et al use the initial formulation proposed by Jimenez; charge and capacitances are written in terms of a variable which depends on the surface potential, and is calculated iteratively at the source and drain ends of the channel. Moldovan uses a charge-based formulation: from a charge control model, developed by B. Iñiguez et al. (Explicit continuous model for long-channel undoped surrounding gate MOSFETs, IEEE Transactions on Electron Devices, August 2005)
from the analysis of D. Jimenez et al, analytical expressions of charges and capacitances are obtained in terms of the mobile charge sheet densities at the source and drain ends of the channel; explicit expressions of the mobile charge sheet denisities are finally used.
Researchers are now addressing the compact modeling of charges and capacitances. In January 2007, in IEEE Transactions on Electron Devices, the first compact model for charges and capacitances of surrounding gate MOSFETs was published: Analytical Charge and Capacitance Models of Undoped Cylindrical Surrounding-Gate MOSFETs, by Moldovan O., Jiménez D., Roig J. and Iñiguez B.
In March 2007, a new charge model for surrounding gate MOSFETs has been published in IEEE Transactions on Electron Devices: Analytic Charge Model for Surrounding-Gate MOSFETs, by Yu B., Lu W.-Y., Lu H. and Taur, Y.
Both models are based on the electrostatic potential soultion obtained by D. Jimenez et al. (Continuous analytic I-V model for surrounding-gate MOSFETs, IEEE Electron Device Letters, August 2005)
from the 1-D Poisson's equation in the radial direction (neglecting the effect of the lateral field). B. yu et al use the initial formulation proposed by Jimenez; charge and capacitances are written in terms of a variable which depends on the surface potential, and is calculated iteratively at the source and drain ends of the channel. Moldovan uses a charge-based formulation: from a charge control model, developed by B. Iñiguez et al. (Explicit continuous model for long-channel undoped surrounding gate MOSFETs, IEEE Transactions on Electron Devices, August 2005)
from the analysis of D. Jimenez et al, analytical expressions of charges and capacitances are obtained in terms of the mobile charge sheet densities at the source and drain ends of the channel; explicit expressions of the mobile charge sheet denisities are finally used.
Mar 6, 2007
Special Compact Modeling Session in the MIXDES'07 Conference
Dr Wladek Grabinski, chair of the MOS-AK Group (MOS Modeling and Parameter Extraction Working Group), is organizing, as in the last years, a Special Compact Modeling Session in the frame of the 14th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES'07).
MIXDES'07 is held in the beautiful town of Ciechocinek (a renowned spa in Poland), 21-23 June 2007. The deadline for regular paper submission is March 12 2007. Prospective authors for the Special Compact Modeling Session should contact Dr. Wladek Grabinski.
MIXDES has become one of the most important microelectronics conferences in Central Europe. Every year an important number of very relevant contributions from all around the world (of course, the majority from Europe) are presented at MIXDES. Prestigeous researchers are invited to give talks for the plenary session and also for the special sessions.
This year, one of the invited presentations, given by myself, will be devoted to the TFT Compact Modeling. It is entitled: "Modeling of Thin Film Transistors for Circuit Simulation"
The Special Compact Modeling Session, held every year under the umbrella of MIXDES, has become a very interesting forum for the discussion and the exchange of information regarding compact modeling issues.
I recommend compact modeling researchers to participate in the MIXDES Special Compact Modeling Session. Contributions are always of very high quality. And I wish to mention that MIXDES has always a superb social programme.
MIXDES'07 is held in the beautiful town of Ciechocinek (a renowned spa in Poland), 21-23 June 2007. The deadline for regular paper submission is March 12 2007. Prospective authors for the Special Compact Modeling Session should contact Dr. Wladek Grabinski.
MIXDES has become one of the most important microelectronics conferences in Central Europe. Every year an important number of very relevant contributions from all around the world (of course, the majority from Europe) are presented at MIXDES. Prestigeous researchers are invited to give talks for the plenary session and also for the special sessions.
This year, one of the invited presentations, given by myself, will be devoted to the TFT Compact Modeling. It is entitled: "Modeling of Thin Film Transistors for Circuit Simulation"
The Special Compact Modeling Session, held every year under the umbrella of MIXDES, has become a very interesting forum for the discussion and the exchange of information regarding compact modeling issues.
I recommend compact modeling researchers to participate in the MIXDES Special Compact Modeling Session. Contributions are always of very high quality. And I wish to mention that MIXDES has always a superb social programme.
Threshold voltage models
As each month, I've been performing a review of some of the more interesting literature. Today, I'll point out three papers, all of them in the current issue of IEEE Trans. El. Devices, and all three of them dedicated to threshold voltage modeling.
The first one is Threshold-Voltage Modeling of Body-Tied FinFETs (Bulk FinFETs), by Choi, B.-K. Han, K.-R. Kim, Y. M. Park, Y. J. Lee, J.-H. Someday I shall comment something about threshold voltage extraction methods, because it is quite interesting. However, this will not be today.
The second paper is Compact Analytical Threshold-Voltage Model of Nanoscale Fully Depleted Strained-Si on Silicon–Germanium-on-Insulator (SGOI) MOSFETs by Venkataraman, V.; Nawal, S.; Kumar, M. J. I think that the title is quite self-explanatory.
Finally, the third one is Analytical Model of the Threshold Voltage and Subthreshold Swing of Undoped Cylindrical Gate-All-Around-Based MOSFETs, by some friends: Hamdy El Hamid; Iniguez, B.; Roig Guitart, J.
There is a point I'd like to make: all of them are dedicated to different devices, using different technologies. This is a demostration that Iroshi Iwai is right when he says that we've got work for still some fourty or fifty years more, and that it will be possible to evade the classic Moore's Law (perhaps it should be called Moore's Guideline).
The first one is Threshold-Voltage Modeling of Body-Tied FinFETs (Bulk FinFETs), by Choi, B.-K. Han, K.-R. Kim, Y. M. Park, Y. J. Lee, J.-H. Someday I shall comment something about threshold voltage extraction methods, because it is quite interesting. However, this will not be today.
The second paper is Compact Analytical Threshold-Voltage Model of Nanoscale Fully Depleted Strained-Si on Silicon–Germanium-on-Insulator (SGOI) MOSFETs by Venkataraman, V.; Nawal, S.; Kumar, M. J. I think that the title is quite self-explanatory.
Finally, the third one is Analytical Model of the Threshold Voltage and Subthreshold Swing of Undoped Cylindrical Gate-All-Around-Based MOSFETs, by some friends: Hamdy El Hamid; Iniguez, B.; Roig Guitart, J.
There is a point I'd like to make: all of them are dedicated to different devices, using different technologies. This is a demostration that Iroshi Iwai is right when he says that we've got work for still some fourty or fifty years more, and that it will be possible to evade the classic Moore's Law (perhaps it should be called Moore's Guideline).
Mar 5, 2007
ESSDERC'07
The 2007 European Solid-State Device Research Conference (ESSDERC) and European Solid-State Circuits Conference (ESSCIRC) will be held in Munich from 11 - 13 September 2007 (about one week before Oktoberfest).
As you may know, ESSDERC is the most prestigeous European conference on electron devices. The acceptance rate is usually less than 50%.
The deadline for paper submissions is April 7 2007.
This year compact modeling appears explicitly as one of the themes for papers to be submitted to ESSDERC:
"Compact, numerical, and physical modeling; device simulation; behavior models; quantum mechanical and non-stationary transport phenomena; ballistic transport; scattering models; process dispersions, parameter fluctuations, variability; TCAD; mixed electrical-thermal modeling and simulation."
Furthermore, on September 14 2007, one day after the end of ESSDERC and ESSCIRC, the MOS-AK Workshop on Compact Modeling will take place.
As you may know, ESSDERC is the most prestigeous European conference on electron devices. The acceptance rate is usually less than 50%.
The deadline for paper submissions is April 7 2007.
This year compact modeling appears explicitly as one of the themes for papers to be submitted to ESSDERC:
"Compact, numerical, and physical modeling; device simulation; behavior models; quantum mechanical and non-stationary transport phenomena; ballistic transport; scattering models; process dispersions, parameter fluctuations, variability; TCAD; mixed electrical-thermal modeling and simulation."
Furthermore, on September 14 2007, one day after the end of ESSDERC and ESSCIRC, the MOS-AK Workshop on Compact Modeling will take place.
Mar 2, 2007
A friend of mine (Oana Moldovan) has sent me a very interesting website: the NanoHUB. As they say: " The nanoHUB, a web-based resource for research, education, and collaboration in nanotechnology, is an initiative of the NSF-funded Network for Computational Nanotechnology (NCN). The NCN is a network of universities with a vision to pioneer the development of nanotechnology from science to manufacturing through innovative theory, exploratory simulation, and novel cyberinfrastructure. NCN students, staff, and faculty are developing the nanoHUB science gateway while making use of it in their own research and education. Collaborators and partners across the world have joined the NCN in this effort."
Great for you! My congratulations for a so nice site!
Great for you! My congratulations for a so nice site!