#paper Z. Ahmed, Q. Shi, Z. Ma, L. Zhang, H. Guo and M. Chan, "Analytical Monolayer MoS2 MOSFET Modeling Verified by First Principle Simulations," in IEEE EDL doi: 10.1109/LED.2019.2952382 https://t.co/CiaNcxqSwb https://t.co/xxTqg2iAMI

#paper Z. Ahmed, Q. Shi, Z. Ma, L. Zhang, H. Guo and M. Chan, "Analytical Monolayer MoS2 MOSFET Modeling Verified by First Principle Simulations," in IEEE EDL
doi: 10.1109/LED.2019.2952382 https://t.co/CiaNcxqSwb pic.twitter.com/xxTqg2iAMI

— Wladek Grabinski (@wladek60) December 16, 2019

from Twitter https://twitter.com/wladek60

December 16, 2019 at 02:22PM
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The Open Source Computer Aided Modeling and Design #devroom schedule for #FOSDEM 2020 is official at: https://t.co/5GpDFo6fpo #paper https://t.co/dkTuVHseGP

The Open Source Computer Aided Modeling and Design #devroom schedule for #FOSDEM 2020 is official at: https://t.co/5GpDFo6fpo #paper pic.twitter.com/dkTuVHseGP

— Wladek Grabinski (@wladek60) December 16, 2019

from Twitter https://twitter.com/wladek60

December 16, 2019 at 11:13AM
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The EKV2.6 MOSFET compact #model has had a considerable impact on the academic and industrial community of ultra low power analog/RF IC design, since its inception in 1996. Its Verilog-A code is available online at GitHub, now https://t.co/0iDmBChDVm https://t.co/BTBAbPm7aN

The EKV2.6 MOSFET compact #model has had a considerable impact on the academic and industrial community of ultra low power analog/RF IC design, since its inception in 1996. Its Verilog-A code is available online at GitHub, nowhttps://t.co/0iDmBChDVm pic.twitter.com/BTBAbPm7aN

— Wladek Grabinski (@wladek60) December 4, 2019

from Twitter https://twitter.com/wladek60

December 04, 2019 at 03:23PM
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[mos-ak] [Final Program] 12th International MOS-AK Workshop; Silicon Valley, Dec.11 2019

12th International MOS-AK Workshop

(co-located with the IEDM and Q4 CMC Meetings)

Silicon Valley, December 11, 2019

<http://www.mos-ak.org/silicon_valley_2019/>

Together with Silvaco team, the MOS-AK workshop host as well as International MOS-AK Board of R&D Advisers and all the Extended MOS-AK TPC Committee, we have the pleasure to invite to consecutive, 12th International MOS-AK Workshop is Silicon Valley.

Scheduled, subsequent 12th MOS-AK SPICE/Compact Modeling Workshop organized in the Silicon Valley, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors. 

The MOS-AK workshop program is available online:

<http://www.mos-ak.org/silicon_valley_2019/>

Venue:

Silvaco 

2811 Mission College Blvd., 6th Floor 

Santa Clara, CA 95054

Online Registration is still open

(any related enquiries can be sent to register@mos-ak.org)

Postworkshop Publications:

Selected best MOS-AK technical presentation will be recommended for further publication
in a special Solid State Electronics issue on compact modeling 

W.Grabinski on the behalf of International MOS-AK Committee

WG02122019

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#Alibaba’s growing #opensource stature - Eyes on APAC https://t.co/W3qBN15Wsr https://t.co/DoR0OSzOMh

#Alibaba’s growing #opensource stature - Eyes on APAC https://t.co/W3qBN15Wsr pic.twitter.com/DoR0OSzOMh

— Wladek Grabinski (@wladek60) December 2, 2019

from Twitter https://twitter.com/wladek60

December 02, 2019 at 04:07PM
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[C4P] 50th ESSDERC / 46th ESSCIRC

Grenoble (F) Sept.14-18 2020

Call for Papers

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits. The level of integration for system-on-chip design is rapidly increasing. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers and system designers is necessary. While keeping separate Technical Program Committees, ESSDERC and ESSCIRC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both communities. Attendees registered for either conference are encouraged to attend any of the scheduled parallel sessions, regardless to which conference they belong.

TPC Tracks:

• Advanced Technology, Process and Materials
• Analog, Power and RF Devices
• Compact modeling and process/device simulation
  
• Joint TRACK: Memory devices and circuits towards non Von Neumann
• Joint TRACK: Emerging Computing Devices and Circuits
• Joint TRACK: Devices and circuits for Sensors, Optoelectronics and Display
  
• Analog Circuits
• Data Converters Circuits
• RF & mmW Circuits
• Frequency Generation Circuits
• Wireless & Wireline Circuits & Systems
• Digital Circuits & Systems
• Power Management Circuits

#paper A. Biswas, D. Ludwig and M. Cotorogea, "A New Computer-Aided Calibration Technique of Physics Based IGBT & Power-Diode Compact Models with Verilog-A Implementation," 2019 SISPAD, Udine, Italy, 2019, pp. 1-4. doi: 10.1109/SISPAD.2019.8870499 https://t.co/tM3k2ejZWs https://t.co/8bzoxK27ru

#paper
A. Biswas, D. Ludwig and M. Cotorogea, "A New Computer-Aided Calibration Technique of Physics Based IGBT & Power-Diode Compact Models with Verilog-A Implementation," 2019 SISPAD, Udine, Italy, 2019, pp. 1-4.
doi: 10.1109/SISPAD.2019.8870499 https://t.co/tM3k2ejZWs pic.twitter.com/8bzoxK27ru

— Wladek Grabinski (@wladek60) November 30, 2019

from Twitter https://twitter.com/wladek60

November 30, 2019 at 06:12PM
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