ngspice release 27, September 17th, 2017 https://t.co/0jSKnj19no #Modeling http://pic.twitter.com/c5INhqX0yD
— Wladek Grabinski (@wladek60) November 7, 2017
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November 07, 2017 at 08:36PM
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Nov 7, 2017
ngspice release 27, September 17th, 2017 https://t.co/0jSKnj19no #Modeling https://t.co/c5INhqX0yD
from Twitter https://twitter.com/wladek60
November 07, 2017 at 08:36PM
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Nov 6, 2017
A Near-Threshold Voltage Oriented Library for High-Energy Efficiency and Optimized Performance in 65nm CMOS https://t.co/OOQYhqgx9U #paper
A Near-Threshold Voltage Oriented Library for High-Energy Efficiency and Optimized Performance in 65nm CMOS https://t.co/OOQYhqgx9U #paper
— Wladek Grabinski (@wladek60) November 6, 2017
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November 06, 2017 at 08:26PM
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Nov 3, 2017
[paper] Validation of MOSFET Model Source–Drain Symmetry
Validation of MOSFET Model Source-Drain Symmetry
Colin C. McAndrew
IEEE TED, Vol. 53, No. 9, Sep. 2006
doi: 10.1109/TED.2006.881005
doi: 10.1109/TED.2006.881005
Abstract: Symmetry around Vds= 0 is a critical requirement for MOSFET models, e.g. as it affects the ability of a model to simulate distortion accurately for some RF CMOS mixers. The Gummel symmetry test (GST) has been the standard test used to evaluate the symmetry of MOSFET models. However, this test is only applicable to DC current, and is only valid when there is negligible gate or substrate current. This paper presents a DC symmetry test that is applicable in the presence of gate and substrate currents, and an AC symmetry test that is simple and effective in verifying symmetry of Cgs and Cgd.
FIG: Biasing scheme for dc symmetry testing.
Nov 2, 2017
Circuit-aging #modeling based on dynamic MOSFET degradation and its verification (#SISPAD) https://t.co/QgJ5UIe7Yx
Circuit-aging #modeling based on dynamic MOSFET degradation and its verification (#SISPAD) https://t.co/QgJ5UIe7Yx
— Wladek Grabinski (@wladek60) November 2, 2017
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November 02, 2017 at 10:43AM
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Analytical #modeling is both science and art https://t.co/DBdMqRJqkU https://t.co/G45cufzKTb
Analytical #modeling is both science and art https://t.co/DBdMqRJqkU http://pic.twitter.com/G45cufzKTb
— Wladek Grabinski (@wladek60) November 2, 2017
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November 02, 2017 at 10:07AM
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#Modeling of flicker noise in quasi-ballistic FETs - IEEE Conference Publication https://t.co/JpropPaK27
#Modeling of flicker noise in quasi-ballistic FETs - IEEE Conference Publication https://t.co/JpropPaK27
— Wladek Grabinski (@wladek60) November 2, 2017
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November 02, 2017 at 10:05AM
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Circuit-aging #modeling based on dynamic MOSFET degradation and its verification - IEEE Conference Publication https://t.co/QnZG525Y7R
Circuit-aging #modeling based on dynamic MOSFET degradation and its verification - IEEE Conference Publication https://t.co/QnZG525Y7R
— Wladek Grabinski (@wladek60) November 2, 2017
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November 02, 2017 at 10:04AM
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