Design Strategies for Ultralow Power 10nm FinFETs
Abhijeet Walkeaa, Garrett Schlenvogtbb, Santosh Kurinecaa
aDepartment of Electrical & Microelectronic Engineering, RIT, New York, USA
bTCAD Application Engineer, Silvaco
Received 12 June 2017, Accepted 19 June 2017, Available online 20 June 2017
Abstract: In this work, new design strategies for 10nm node NMOS bulk FinFET transistors are investigated to meet low power (LP) (20pA/μm< I
OFF <50pA/μm) and ultralow power (ULP) (I
OFF <20pA/μm) requirements using three dimensional (3D) TCAD simulations. The punch-through stop implant, source and drain junction placement and gate workfunction are varied in order to study the impact on the OFF-state current (I
OFF), transconductance (g
m), gate capacitance (C
gg) and intrinsic frequency (
fT). It is shown that the gate length of 20nm for the 10nm node FinFET can meet the requirements of LP transistors and ULP transistors by source-drain extension engineering, punch-through stop doping concentration, and choice of gate workfunction.
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https://doi.org/10.1016/j.sse.2017.06.012]