Feb 28, 2017

[mos-ak] [Final Program] Spring MOS-AK Workshop at DATE Conference in Lausanne, March 31, 2017

 Spring MOS-AK Workshop  
   at DATE Conference in Lausanne, March 31, 2017
     Final Program online http://mos-ak.org/lausanne_2017/   
 
 Together with the MOS-AK workshop chair, Dr. Jean-Michel Sallese, EPFL and International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) as well as all the Extended MOS-AK TPC Committee, we have pleasure to invite to the Spring MOS-AK Workshop which will be held during DATE Conference on March 31, 2017 in Lausanne (CH). The MOS-AK workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Important Dates:
  • Preannouncement - Dec. 2016
  • Call for Papers - Jan. 2017
  • Final Workshop Program - Feb. 2017
  • MOS-AK Workshop - March 31, 2017
Venue:
Swisstech Convention Centre Quartier Nord de l'EPFL Route Louis-Favre 2 CH-1024 Ecublens (CH)
Final Program of Spring MOS-AK/DATE workshop is available online
http://www.mos-ak.org/lausanne_2017/

Online MOS-AK/DATE Workshop Registration
https://www.date-conference.com/registration
(any related inquiries can be sent to register@mos-ak.org)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee

WG280217

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[ngspice] FM Bugger Circuit

Project Summary by https://www.eeweb.com
The project circuit design is a FM Bugger circuit. It works like a transmitter that transmits and projects information signals into the air wherein a FM radio will act as a receiver which would receive the transmitted signal. The circuit and the FM radio must be tuned-in with the same frequency to be able to transmit and receive information in the same channel. The FM bugger circuit is originally designed to be used like a spy gadget to eavesdrop other people’s conversations. Though it is designed that way, it is pretty much useful as a transmitter or as a walkie-talkie to relay messages in a distance [read more...]

Testing and Design Procedure
The FM bugger circuit is tested using PartSim and the NGSpice to test the output of the circuit:


FM Bugger Circuit Simulation
R1 Net1009 Mic 22K
R2 Net1009 Net1016 47K
R3 Net1003 0 33K
C1 Net1016 Mic 1NF
C2 Net1016 0 1NF
C3 Net1002 Net1003 4.7pF
C4 Net1002 Antenna 1NF
C5 Net1009 0 22NF
C6 Net1009 Net1002 50pF
L1 Net1009 Net1002 9NH
Q1 Net1002 Net1016 Net1003 2N2222
V1 Net1009 0 3V
V2 Mic 0 SINE ( 1 1 20Khz 0.0S )
R4 0 Antenna 1K
.options rshunt = 1.0e12 KEEPOPINFO
.MODEL 2N2222 NPN IS =3.0611E-14 NF =1.00124
+ BF =220 IKF=0.52 VAF=104 
+ ISE=7.5E-15 NE =1.41 NR =1.005 BR =4 
+ IKR=0.24 VAR=28 ISC=1.06525E-11 NC =1.3728 RB =0.13 
+ RE =0.22 RC =0.12 CJC=9.12E-12 MJC=0.3508 VJC=0.4089 
+ CJE=27.01E-12 TF =0.325E-9 TR =100E-9
.control
OP
write Net1002 Net1003 Net1009 Net1016 Mic Antenna I(V1) I(V2)
set appendwrite true
rusage everything
.endc
.end
Conclusion
The simulation of the FM bugger circuit in PartSim shows that the circuit is working. The microphone was assumed to have an input of a 20 kHz sinusoidal wave. Then, the output signal at the load, R4 assumed to be the antenna for the circuit, turns out to produce a FM signal. Therefore, the FM bugger circuit itself has a great possibility to succeed and operate in real

Project Links:
http://www.schematics.com/embed/fm-bugger-circuit-36638/
http://www.pcbweb.com/projects/DqEwZcNdcy3ddghPnJefdJIzTcWqLd



[paper] Readout electronics for LGAD sensors

Readout electronics for LGAD sensors
O. Alonso,a N. Franch,a J. Canals,a F. Palacio,a M. López,a A. Vilà,a A. Diéguez,a
M. Carulla,b D. Flores,b S. Hidalgo,b A. Merlos,b G. Pellegrinib and D. Quirionb
aDepartment of Engineering: Section of Electronics, University of Barcelona,
C/ Martí i Franquès nº1, Barcelona, 08028 Spain
bInstituto de Microelectrónica de Barcelona — Centro Nacional de Microelectrónica (IMB-CNM),
Campus UAB, Cerdanyola del Vallès, Bellaterra, Barcelona, 08193 Spain
doi:10.1088/1748-0221/12/02/C02069

Abstract: In this paper, an ASIC fabricated in 180 nm CMOS technology from AMS with the very front-end electronics used to readout LGAD sensors is presented as well as its experimental results. The front-end has the typical architecture for Si-strip readout, i.e., preamplification stage with a Charge Sensitive Amplifier (CSA) followed by a CR-RC shaper. Both amplifiers are based on a folded cascode structure with a PMOS input transistor and the shaper only uses passive elements for the feedback stage. The CSA has programmable gain and a configurable input stage in order to adapt to the different input capacitance of the LGAD sensors (pixelated, short and long strips) and to the different input signal (depending on the gain of the LGAD). The fabricated prototype has an area of 0.865mm  0.965mm and includes the biasing circuit for the CSA and the shaper, 4 analog channels (CSA+shaper) and programmable charge injection circuits included for testing purposes. A first approach to find the proper dimensioning of the input transistor has been done using a Matlab script, where the transconductance value has been calculated with the EKV model

Acknowledgments This work has been partially funded by the Spanish national projects FPA2013-48387 and FPA2015-71292. In addition, this work has been done in the framework of RD50 CERN collaboration.

Feb 21, 2017

1-cent "lab on a chip" could save lives

Rahim Esfandyarpour, Stanford University, helped to develop a way to create a diagnostic "lab on a chip" for just a penny:
"I'm pretty sure it will open a window for researchers because it makes life much easier for them - just print it and use it," said Esfandyarpour. The results of this research were recently published in the journal Proceedings of the National Academy of Sciences [Source: Stanford Medicine]

[paper] Bipolar and MOS Transistors Under the Effect of Radiation

Measurements of the Electrical Characteristics of Bipolar and MOS Transistors
Under the Effect of Radiation
K. O. Petrosyants, L. M. SamburskiiI. A. KharitonovM. V. Kozhukhov
Meas Tech (2017) doi:10.1007/s11018-017-1100-z

ABSTRACT: The specific nature of the process of measuring the electrical characteristics of bipolar and metal-oxidesemiconductor (MOS) transistors subjected to the action of neutron, electron, and gamma irradiation is considered. An automated measurement system is developed. Examples illustrating the use of the system for investigations of the radiation hardness of transistors are presented and the parameters of SPICE models for use in circuit design (including SOI/SOS CMOS circuits with EKV-RAD macromodel) are determined.

Translated from Izmeritel’naya Tekhnika, No. 10, pp. 55–60, September, 2016 [read more...]

Feb 17, 2017

[call for papers] 2017 IEEE S3S Conference

S3S Conference 2017
Overview: This industry - wide event has gathered, for over 30 years, industry leaders and widely known experts, in a social - oriented environment. Our contributed papers and invited talks are focused on SOI Technology, Low - Voltage Devices/Circuits/Architectures, and 3D Integration. These 3 technologies will play a major role in tomorrow's industry as they enable application - tailored and Energy / Cost efficient circuit designs.
Important Dates
Paper Submission Deadline: May 22, 2017
Acceptance Notification: July 1, 2017

The conference at a glance
Monday to Wednesday, Oct. 16-18, 2017: Technical Sessions
Thursday, Oct.19: Fully - Depleted SOI Circuit Design; Full-day Tutorial
Tuesday, Oct.17: Monolithic 3D Half-day Tutorial

Scope: We welcome papers in the following areas:
Silicon On Insulator (SOI)
• Advanced Materials, Substrate and Processes
• Device Physics, Characterization and Modeling
• Device/Circuit Integration
• SOI Design, Circuits and Applications
• Non-Digital Devices and Applications (RF,
HV, Photonics, NEMS, MEMS, Analog...)
• New SOI Structures, Circuits and Applications
Low-Voltage Microelectronics
• Space-Based and Unattended Remote Sensors
• Biomedical Devices
• Low-Voltage Handheld/wireless systems
• Ultra-Low-Power Digital Computation
• Analog and RF Technologies
• Low Voltage Memory Technologies
• Energy Harvesting Techniques
• Asynchronous Circuits
• Novel Device and Fabrication Technology
3D Integration
• Low Thermal Budget Processing
• Fabrication Techniques and Bonding Methods
• Design and Test Methodologies
• Processes for Multi Wafer Stacking
• 3D IC EDA and Design Technology
• Heterogeneous Structures
• 3D Manufacturing and Logistics
• Reliability of 3D Circuits
• Fault Tolerant 3D Designs

Paper Submission:
Prospective authors should prepare a 2page abstract (follow online guidelines).
Acceptance is based on paper’s technical quality and relevance.

Conference manager contact Joyce Lloyd
6930 De Celis Pl., #36
Van Nuys, CA 91406
Tel: +1 818 795 3768
Fax: +1 818 855 8392

Feb 16, 2017

HiSIM-HV and HiSIM2 implemented into ngspice

ngspice (Open Source SPICE Circuit Simulator) supports latest versions of HiSIM_HV and HiSIM2 [read more...]
REF: 
[2] T. Ezaki, D. Navarro, Y. Takeda, N. Sadachika, G. Suzuki, M. Miura-Mattausch, H. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, and S. Miyamoto, “Non-quasi-static Analysis with HiSIM, a Complete Surface-potential-based MOSFET Model”, Proceedings of the 12 th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES’2005), 923-928 (2005.6), Invited Paper
[3] M. Miura-Mattausch, D. Navarro, Y. Takeda, H.J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi and S. Miyamoto, “MOSFET Modeling for RF Circuit Era”, Proceedings of the 11 th International Conference on Mixed Design Mixed Design of Integrat ed Circuits and Systems (MIXDES’2004), 62-66 (2004), Invited Paper
[5] Mattausch,  H.J.;  Umeda,  T.;  Kikuchihara,  H.;  Miura-Mattausch,  M.,  "The  HiSIM compact models of high-voltage/power semiconductor devices for circuit simulation," in Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on , vol., no., pp.1-4, 28-31 Oct. 2014
[6] Mattausch,  H.J.;  Miyake,  M.;  Ii zuka,  T.;  Kikuchihara,  H.;  Miura-Mattausch,  M.,  "The Second-Generation  of  HiSIM_HV  Compact  Models  for  High-Voltage  MOSFETs,"  in Electron Devices, IEEE Transactions on , vol.60, no.2, pp.653-661, Feb. 2013