2016 Phil Kaufman Award Recipient: Dr. Andrzej Strojwas

Kaufman Award Dinner: Why you should Attend

IEEE’s CEDA and the ESD Alliance – with help from their friends at PDF Solutions, Cadence, Mentor, Synopsys and ACM SIGDA – will host a dinner on Thursday, January 26th, in honor of the 2016 Phil Kaufman Award recipient: Dr. Andrzej Strojwas, Keithley Professor of ECE at Carnegie Mellon and long-time CTO at PDF Solutions.

This year’s Kaufman Award Dinner promises to be an inspiring evening, one that will help you remember why you went to work here in the first place [read more...]

If you want to attend, you can register here.

[mos-ak] [2nd Announcement and Call for Papers] Spring MOS-AK Workshop at DATE Conference in Lausanne, March 31, 2017

 Spring MOS-AK Workshop  

   at DATE Conference in Lausanne, March 31, 2017
     2nd Announcement and Call for Papers   

 
 Together with the MOS-AK workshop chair, Dr. Jean-Michel Sallese, EPFL and International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) as well as all the Extended MOS-AK TPC Committee, we have pleasure to invite to the Spring MOS-AK Workshop which will be held during DATE Conference on March 31, 2017 in Lausanne (CH). Planned MOS-AK workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Important Dates:

• Preannouncement - Dec. 2016
  
• Call for Papers - Jan. 2017
  
• Final Workshop Program - Feb. 2017
  
• MOS-AK Workshop - March 31, 2017

Venue:

Swisstech Convention Centre Quartier Nord de l'EPFL Route Louis-Favre 2 CH-1024 Ecublens (CH)

Topics to be covered include the following among other related to the compact/SPICE modeling :

• Compact Modeling (CM) of the electron devices
  
• Advances in semiconductor technologies and processing
  
• Verilog-A language for CM standardization
  
• New CM techniques and extraction software
  
• Open Source TCAD/EDA modeling and simulation
  
• CM of passive, active, sensors and actuators
  
• Emerging Devices, TFT, CMOS and SOI-based memory cells
  
• Microwave, RF device modeling, high voltage device modeling
  
• Nanoscale CMOS devices and circuits
  
• Technology R&D, DFY, DFT and reliability/ageing IC Designs
  
• Foundry/Fabless Interface Strategies
  

Online MOS-AK Abstract Submission:
Prospective authors should submit abstract online 

http://www.mos-ak.org/lausanne_2017/abstracts.php

(any related inquiries can be sent to abstrscts@mos-ak.org)

Online Workshop Registration (to be open Feb.2017):

http://www.mos-ak.org/lausanne_2017 
(any related inquiries can be sent to register@mos-ak.org)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee

WG17012017

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[mos-ak] [press note] 9th International MOS-AK Workshop at UC Berkeley, Dec.7, 2016

Arbeitskreis Modellierung von Systemen und Parameterextraktion 

Modeling of Systems and Parameter Extraction Working Group

9th International MOS-AK Workshop

(co-located with the CMC Meeting and IEDM Conference)

December 7, 2016 Berkeley

The MOS-AK Association, a global compact/SPICE modeling and Verilog-A standardization forum, held its annual Q4 event on December 7, 2016 UC Berkeley as its 9th consecutive International MOS-AK Workshop. The event was coordinated by Larry Nagel, OEC (USA) and Andrei Vladimirescu, UCB (USA); ISEP (FR) representing the International MOS-AK Board of R&D Advisers. The workshop was hosted by Prof. Jaijeet Roychowdhury of EECS at the University of California at Berkeley and co-sponsored by Keysight Technologies and NEEDS of nanoHUB.org.

The workshop provided presentations from the leading developers of compact device models. The audience spanned the full range of the semiconductor industry, including representatives from foundries, model characterization services firms, academic researchers investigating emerging device technologies, and design companies. The amount and breadth of technical information discussed was vast -- here are but a few highlights by ChipGuy:
<https://www.semiwiki.com/forum/content/6542-its-all-about-models.html>

These were but a few of the technical highlights and achievements discussed at the workshop which are available online:
<http://www.mos-ak.org/berkeley_2016>

The MOS-AK Modeling Working Group has various deliverables and initiatives, including: a book entitled "Open Source CAD Tools for Compact Modeling" <www.mos-ak.org/books>; an open Verilog-A directory with compact models <http://www.mos-ak.org/open_dir/>; and supporting FOSS TCAD/CAD software.

The MOS-AK Association plans to continue its standardization efforts by organizing additional compact modeling meetings, workshops and courses in Europe, USA, India and China throughout 2017 year, including:

• Spring MOS-AK Workshop in Lausanne at DATE Conference (March 31 2017) 
  <http://www.mos-ak.org/lausanne_2017>
  
• 2nd Sino MOS-AK Workshop in Hangzhou (June 2017) 
  <http://www.mos-ak.org/hangzhou_2017>
  
• 15th MOS-AK ESSDERC/ESSCIRC Workshop in Leuven (Sept.11, 2017) 
  <http://www.mos-ak.org/leuven_2017>

If you are involved in developing or supporting device models for circuit designers, we would encourage you to become an active participant in the MOS-AK community.

About MOS-AK Association:
MOS-AK, an international compact modeling association primarily focused in Europe, to enable international compact modeling R&D exchange in the North/Latin Americas, EMEA and Asia/Pacific Regions. The MOS-AK Modeling Working Group plays a central role in developing a common language among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact/SPICE modeling and its Verilog-A standardization and related CAD/EDA tools for the compact models development, validation/implementation and distribution.

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[paper] Radiation-Induced Fault Simulation of SOI/SOS CMOS LSI’s Using Universal Rad-SPICE MOSFET Model

Radiation-Induced Fault Simulation of SOI/SOS CMOS LSI’s 

Using Universal Rad-SPICE MOSFET Model

Konstantin O. Petrosyants, Lev M. Sambursky, Igor A. Kharitonov, Boris G. Lvov

J Electron Test (2017)

doi:10.1007/s10836-016-5635-8

Abstract: The methodology of modeling and simulation of environmentally induced faults in radiation hardened SOI/SOS CMOS IC’s is presented. It is realized at three levels: CMOS devices – typical analog or digital circuit fragments – complete IC’s. For this purpose, a universal compact SOI/SOS MOSFET model for SPICE simulation software with account for TID, dose rate and single event effects is developed. The model parameters extraction procedure is described in great depth taking into consideration radiation effects and peculiarities of novel radiation-hardened (RH) SOI/SOS MOS structures. Examples of radiation-induced fault simulation in analog and digital SOI/SOS CMOS LSI’s are presented for different types of radiation influence. The simulation results show the difference with experimental data not larger than 10–20% for all types of radiation.

The electrical schematics of SOS CMOS opamp and 4-bit counter are presented; two variants of either macromodel were used for body-tied partially-depleted transistors: a) core EKV-SOI/ BSIMSOI model; b) EKV-RAD/ BSIMSOI-RAD macromodel. [read more...]

ICMTS 2017 in Grenoble (F)

30th International Conference on Microelectronic Test Structures 

March 27-30, 2017, MINATEC, Grenoble (F)

• Monday 27th March
• Tutorials
• Welcome Reception
• Tuesday 28th March
• SESSION 1: Novel Test Structure
• SESSION 2: Novel Materials
• SESSION 3: Variability
• SESSION Exhibitions
• Wednesday 29th March
• SESSION 4: Device Modeling
• SESSION 5: RF and HV
• SESSION 6: Device Testing
• SESSION 7: Sensor Test Structures
• Thursday 30th March
• SESSION 8: Low Frequency Noise
• SESSION 9: Advanced Test Methods

[read more...]

[paper] Modeling, simulation and implementation of circuit elements in an open-source tool set on the FPAA

Modeling, simulation and implementation of circuit elements in an open-source tool set on the FPAA

Aishwarya Natarajan and Jennifer Hasler

Georgia Institute of Technology Atlanta USA

Analog Integr Circ Sig Process (2017), pp 1–12

doi:10.1007/s10470-016-0914-y

ABSTRACT: An open-source simulator to design and implement circuits and systems, replicating the results from the Field Programmable Analog Array (FPAA) is presented here. The fundamental components like the transistors, amplifiers and floating gate devices have been modeled based on the EKV model with minimal parameters. Systems including continuous-time filters and the analog front-end of a speech processing system have been built from these basic components and the simulation results and the data from the FPAA are shown. The simulated results are in close agreement to the experimental measurements obtained from the same circuits compiled on the FPAA fabricated in a 350 nm process [read more...]

On Layout Tools and others

A while ago SolvEx Group has posted a blog note on the Layout Tools, including the open source ones, too. There are also a few questions which are worth to review again:

1. How is Layout different from Placement and Route?
2. What is the difference between Synopsys Astro and Cadence Virtuoso-do they offer layout or are just placement and routing tools? (Comparing them with Magic and LASI)!
3. What is the intermediate map/snapshot/diagram - which we can use and create a complete chip out of? For example after seeing the Chip and reverse engineering the same- what is that something which I can use to create my own chip in the foundry? Reference - Chinese Mobile chips. They do the same-as they bypass the flow for design entry/verification/simulation/floor planning etc and release the chip within a few hrs of seeing the original chip(say famous case of duplicating iPhone/Nokia in the Chinese markets)
4. Are Stick Diagrams passed to the Foundry or else what is the base unit that is given to Foundry as an input to be manufactured as a chip.
5. Giving below a collection all possibly available Layout Tools (Categorized as Open Source, Cheap, Expensive)

Open source software	Description	Web site
wol	Wol is a graphical environment for IC mask layout	http://www.cs.berkeley.edu/~lazzaro/chipmunk/describe/wol.html
toped	Micron based layout editor with extensive scripting capabilities. Under active development and part of Fedora Electronic Lab.	http://www.toped.org.uk
microwind3	Lambda based layout editor especially adapted for interactive design with Spice. This used to be completely free, but now only a Lite version is.	http://www.microwind.org
magic	Lambda based layout editor with good options for writing CIF and/or GDS files. Supports scripting. Large user base. Part of Fedora Electronic Lab. Used for extraction and CIF/GDS creation by the pharosc libraries	http://opencircuitdesign.com/magic
lasi	LASI stands for LAyout Software for Individuals. It is designed to run on Windows, though it also runs on Linux under Crossover Office. Actively used software with frequent updates.	http://lasihomesite.com
kic	Part of open source packages released by Whiteley Research.	http://wrcad.com/freestuff.html
graal	Lambda based layout editor allowing conversion to CIF and GDS with appropriate technology files. Dreal is the companion software to view CIF and GDS. Part of a tool set from Alliance which is probably the best open-source software for IC design. Comes with own standard cell library. Part of Fedora Electronic Lab. The pharosc standard cells are drawn with graal.	http://www-asim.lip6.fr/recherche/alliance
electric	Comprehensive set of software programs designed around the concept of silicon compilation. Version 6 crashed a lot, and stored all design data in a single file which exposed one to the risk of file corruption and loss of all data (I speak from experience). New version written in Java. Extensive documentation.	http://www.staticfreesoft.com/productsSoftware.html
dreal	Simple layout editor which uses CIF or GDS as its native format. Companion software is Graal.	http://www-asim.lip6.fr/recherche/alliance
Cheap software
xic	Whiteley Research Inc. Layout editor with linked Spice simulator. List price is $1195.	http://www.wrcad.com/xic.html
slam-edit	Stabie-Soft Inc. Unix/Linux based layout editor. It seems a licence cannot be purchsed, only leased for one year periods (bad if the company folds). List price on web site is $2,000 per year.	http://www.stabie-soft.com/sledit.html
ledit	Tanner Research Inc. Windows only layout editor popular with mixed signal designers. Ledit sed to cost $1,000, but this price could not be verified (which is surprising since low price is a key selling point of the software).	http://www.tanner.com/EDA/product/Tools_PhysicalLayout.html
layedpro	Mycad Inc. Windows only layout editor designed in Korea but supported for English language users from California. No new product since 2005 on US site, but Korean site seems active. No price could be confirmed.	http://www.mycad.com/02pro/01.html http://www.mycad.co.kr
layed	Catena Software GmbH. Demo versions for Linux and Windows can be downloaded. List price of the basic editor might be €1,585 (could not be recently verified).	http://www.catena-ffo.de/laytools.htm
iced	IC Editors Inc. Windows only editor that used to cost $2,750. Now it is free but with a restrictive licence. Work is on-going to open source it which might make it available under Linux (although the Windows drawing primitives would need to be replaced with GTK).	http://www.iceditors.com
Expensive software
virtuoso	Cadence Design Systems, Inc. The market leader. The price might be $40,000 to lease for one year.	http://www.cadence.com/products/custom_ic/veditor/index.aspx
max	Micro Magic Inc. Looks like a commercial version of Magic. Price is $30,000 for a one year licence. Despite the fancy price tag, something was freely downloadable from the web in the 2004 timeframe.	http://www.micromagic.com
laker	Silicon Canvas Inc. Linux and Unix based editor. Top of the line laker-ddl is $70,000 for a one year licence. Regular Laker 3 is $35,000 for a one year licence.	http://www.sicanvas.com
icstation	Mentor Graphics Corp. No public pricing information could be found.	http://www.mentor.com/cicd/icstation.html