Nov 18, 2016

INFOS 2017 in Potsdam, Germany

20th Conference on “Insulating Films on Semiconductors” 
INFOS 2017
June 27th – 30th, 2017 in Potsdam, Germany

The INFOS conference is a prestigious biennial event which brings together electrical engineers, technologists, materials scientists, device physics and chemists from Europe and around the world to debate the latest development in thin insulating film technology and identify as well as address challenges ahead in this highly diversifying field [read more...]

Conference Topics:
  • High-k dielectrics, metal gate materials and SiO2 for future scaling
  • Gate stack materials for high mobility substrates (Ge, SiGe, GaN, III-V)
  • Stacked dielectrics for non-volatile memory (flash, nc-Si)
  • Dielectrics for resistive switching memories and spin memories
  • Dielectrics for DRAM and MIM
  • Low-k dielectrics
  • Semiconductors on insulators
  • Dielectrics for 2D materials, nanowires, 2D devices and carbon-based devices
  • Surface cleaning technologies
  • Physics and chemistry of dielectrics and defects
  • Characterization techniques for dielectrics and interfaces
  • Electrical reliability, leakage and modelling
  • Modelling of atomic structure of dielectrics, interfaces and thin films
  • Topological insulators
  • Ferroelectrics and functional oxides
  • Dielectrics and thin films for TFT, amorphous or organic devices and photovoltaics
  • Dielectrics for photonics and sensing

Creating A PCB In Everything: KiCad, Part 1 https://t.co/gSqz7GGbnE #todo #feedly #papers


from Twitter https://twitter.com/wladek60

November 17, 2016 at 11:23PM
via IFTTT

Nov 16, 2016

Open Source License Compliance bei Embedded-Systemen

Open Source License Compliance bei Embedded-Systemen 
( Kompaktseminar, ESE Kongress 2016, in Sindelfingen )
Referent: Dr. Till Jaeger, JBB Rechtsanwälte
Zeit: 28.11.16 09:00-12:30


Abstract: When using Linux and other open source software (OSS), the license terms of the GPL and other open source licenses must be adhered to. As license violations lead directly to copyright infringements, appropriate compliance measures are necessary. The compact seminar presents the essential requirements for a compliance process based on the OpenChain Initiative. OpenChain aims at an international standard for suppliers using OSS in your products.

Outline:
  1. What is Open Source Software?
  2. How does the open source license model work?
  3. Legal consequences of violation of OSS license terms
  4. How is it ensured that the use of OSS is known and which licensing conditions are affected?
  5. The Copyleft (1): When must self-development be released again as OSS?
  6. Copyleft (2): Verification of license compatibility between different OSS licenses
  7. Process to comply with sales obligations (for example, source code offer, co-delivery license texts)
  8. Methods of quality control


[read more...]


National Workshop on Advanced Nanoscale Device Design Using TCAD

The National Workshop on Advanced Nanoscale Device Design Using Technology Computer-Aided Design (TCAD) was organized by the IEEE SolidState Circuits Society (SSCS) College of Engineering Chengannur, India Chapter. The workshop was held 28 December 2015 through 1 January 2016 as a three-day tutorial and two-day handson session. The event was graced with the presence of distinguished lecturers from top institutions in India, including Prof. Yogesh S. Chouhan from IIT Kanpur delivering the keynote talk. The workshop attracted approximately 150 participants from 15 reputable academic institutions. People from industry and also attended the event.
The coordinators were proud to present a successful workshop as one of the first events since the formation of the Chapter. The event was funded by the SSCS extra subsidy program. The feedback received from the attendees was very positive. Each participant received a certificate during the closing ceremony of the event. The five-day workshop came to an end by the heartfelt vote of thanks by Nisha Kuruvilla, with a motto “This is just the beginning.” [read more...]

Nov 15, 2016

[paper] Analysis of aging effects - From transistor to system level

Analysis of aging effects - From transistor to system level
Maike Taddiken*, Nico Hellwege, Nils Heidmann, Dagmar Peters-Drolshagen, Steffen Paul
Institute of Electrodynamics and Microelectronics,
University of Bremen, Otto-Hahn-Allee 1, Bremen 28359,Germany

ABSTRACT: Due to shrinking feature sizes in integrated circuits, additional reliability effects have to be considered which influence the functionality of the system. These effects can either result from the manufacturing process or external influences during the lifetime such as radiation and temperature. Additionally, modern technology nodes are affected by time-dependent degradation i.e. aging. Due to the age-dependent degradation of a circuit, processes on the atomic scale of the semiconductor material lead to charges in the oxide silicon interface of CMOS devices, altering the performance parameters of the device and subsequently the behavior of the circuit. With the continuous downscaling of modern semiconductor technologies, the impact of these atomic scale processes affecting the overall system characteristics becomes more and more critical. Therefore, aging effects need to be assessed during the design phase and actions have to be taken guaranteeing the correct system functionality throughout a system’s lifetime. This work presents methods to investigate the influence of age-dependent degradation as well as process variability on different levels. An operating-point dependent sizing methodology based on the gm/ID method extended to incorporate aging, which aims at developing aging-resistent circuits is presented. The basic idea of the gm/ID sizing method is the dependence of the operating point of a MOS transistor on the state of inversion in the channel, its strong relation to circuit performance and the possibility to calculate transistor dimensions.The inversion coefficient IC is a fundamental metric within the gm/ID method and numerically represents the inversion level of a MOS device formally described in the EKV MOS model. Additionally, the sensitivity of circuit performances in regard to aging can be determined. In order to investigate the reliability of a complex system on behavioral level, a modeling method to represent the performance of system components in dependence of aging and process variability is introduced. [read more...]

Nov 11, 2016

ICNF 2017: 2nd Call for Papers

24th International Conference on Noise and Fluctuations (ICNF 2017) 
20-23 of June 2017 in Vilnius, Lithuania

We would like to invite you to submit your abstracts. For submission of the abstracts, please, REGISTER and go to the Abstract submission site. Instruction for authors and templates for abstract preparation can be found and downloaded  at the Conference website: http://www.icnf2017.ff.vu.lt/paper-submission/instructions-for-authors
Deadline of the abstract submission is 22 January, 2017

Please also keep in mind ICNF2017 important dates:
  • Abstract submission deadline: 22 January, 2017
  • Notification of acceptance deadline: 27 February, 2017
  • Full paper submission deadline:27 March, 2017
  • Early bird registration: 19 April, 2017
  • Conference: 20-23 June, 2017
Please share this information to your colleagues and those who might be interested in ICNF 2017.

For more information visit the Conference website: http://www.icnf2017.ff.vu.lt/
or contact us: icnf2017@ff.vu.lt

Looking forward to meeting you in Vilnius.

With best regards,
Sandra PralgauskaitÄ— and Paulius Sakalas - Organizing Committee Chairs


Nov 10, 2016

[mos-ak] [Final Program] 9th International MOS-AK Workshop Berkeley DEC.7, 2016

9th International MOS-AK Workshop  
  Berkeley December 7, 2016 
    Final Workshop Program 
 
Together with the MOS-AK workshop host, Prof. Jaijeet Roychowdhury, UCB and International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) as well as all the Extended MOS-AK TPC Committee, we have pleasure to invite to the 9th International MOS-AK Workshop which will be held at EECS Department, University of California, Berkeley on December, 7, 2016. Planned MOS-AK workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Important Dates:
  • Preannouncement - Sept. 2016
  • Call for Papers - Oct. 2016
  • Final Workshop Program - Nov. 2016
  • MOS-AK Workshop - Dec. 7 2016
    •   9:00-12:00 Morning Session
    • 13:00-16:00 Afternoon Session
Venue:
540 Cory Hall 
EECS Department
University of California, Berkeley
Directions to the DOP Center in Cory Hall
See also http://www.eecs.berkeley.edu/Directions/
Final MOS-AK/Berkeley Workshop Program Online 
http://www.mos-ak.org/berkeley_2016/

Online Workshop Registration:
http://www.mos-ak.org/berkeley_2016/registration.php
(any related inquiries can be sent to register@mos-ak.org)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee

WG10112016

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