Oct 15, 2013

[mos-ak] note in the IEEE EDS REGIONAL AND CHAPTER NEWS

REGIONAL AND CHAPTER NEWS
ED Germany – by Joachim N. Burghartz 

The German Chapter of IEEE EDS sponsored the annual spring compact modeling workshop of the MOS-AK/GSA Modeling Working Group, a global compact modeling standardization forum, held April 11– 12, 2013. The meeting was supported by Prof. Doris Schmid-Landsiedel and the staff of the Institute for Technical Electronics, TUM, Munich, who is one of the local coordinators of the ED German Chapter. More than 30 international academic researchers and modeling engineers attended three sessions to listen to 12 technical compact modeling presentations. As in previous years this well-established effort has been coordinated by Wladek Grabinski, Switzerland. The workshop's three sessions focused on common compact modeling actions. Sessions included: (i) How to consolidate and build consistent simulation hierarchy at all levels of advanced TCAD numerical modeling; (ii) Compact/ SPICE modeling for Analog / Mixed Signal circuits; and (iii) Corner modeling and statistical simulations. The MOS-AK/GSA speakers were K.-W. Pieper (Infineon), M. Sylvester (MunEDA), B. Iñiguez (URV), I. Nickeleit (Agilent), L. Heiss (LTE, TUM); T. Schulz (Intel), C. Jungemann (RWTH), M. Brinson (London Metropolitan University), B.-Y. Nguyen (SOITEC), A. Kloes (THM), U. Monga (Intel), and M. Bucher (TUC). The event was accompanied by a series of the software/hardware demos by MOS-AK/GSA industrial partners: Agilent, MunEDA and Tanner EDA. The session technical and software/ hardware demo presentations are available for download at: <http:// www.mos-ak.org/munich_2013/>. 

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Oct 2, 2013

OBip: Open Bipolar Workshop at BCTM in Bordeaux

Open Workshop on European Bipolar related projects: 
Abstract: In Europe, a huge effort is actually undertaken to strengthen Europe's leading edge position in SiGe HBT technology and modeling as well as SiGe enabled mm-wave applications thanks to two European projects that are: DOTSEVEN which aims to achieve HBTs with cut-off frequencies (fmax) of around 700 GHz and RF2THz which aims at the establishment of a 300mm BiCMOS Silicon technology platform for emerging RF, mm-wave and THz consumer applications, as well as Si photonics integration. During this common workshop the main achievements of these projects will be presented.

Opening and Welcome (8:15 AM), Thomas Zimmer, University  Bordeaux 1

Session 1: Technology (8:30 - 10:30 AM)
Alexander Fox, IHP (8:30 - 9:10 AM)
   SiGe HBT Technology Development in the DOTSEVEN  Project
Pascal Chevalier, ST Microelectronics (9:10 - 9:50 AM)
   A 55-nm BiCMOS Platform for Optical and Millimeter-Wave  Systems-on-Chip
Dieter Knoll, IHP (9:50 – 10:30 AM)
   BiCMOS integration of photonic components
Coffee break
Session 2: Modelling and Characterization (11:00 AM – 1:00 PM)
Andreas Pawlak, Univ. of Dresden (11:00 – 11:40 AM)
   Latest developments of HICUM/L2 for mm-wave applications
Bertrand Ardouin, XMOD Technologies (11:40 – 12:20 AM)
   Tools and environment for Sub-THz circuit design
Sebastien Fregonese, CNRS (12:20 AM – 1:00 PM)
   Electro-Thermal Device Characterization & Modelling
Lunch break
Session 3: Design and demonstrator (2:00 – 4:00 PM)
Marco Spirito, University of Delft (2:00 – 2:40 PM)
   Building blocks and system architecture for mm-wave imaging radar
Olivier Tesson, NXP (2:40 – 3:20 PM)
   Passive integration and Packaging for mm-wave applications
Wolfgang Templ, Alcatel Lucent (3:20 – 4:00 PM)
   Application Scenarios from RF2THz

4:00: End of the Open Bipolar Workshop OBip

[read more: 3rd Day Workshop: Special European Dot 5/Dot 7 Workshop]

Sep 30, 2013

[mos-ak] Call for Papers] 6th International MOS-AK/GSA Workshop Dec. 11, 2013 Washington DC

Together with the Organizing Committee and Extended MOS-AK/GSA TPC Committee, we have pleasure to invite to the 6th International MOS-AK/GSA Workshop Dec. 11, 2013 Washington DC. The specific workshop goal will be to classify the most important directions for the future development of the electron device models, not limiting the discussion to compact models, but including physical, analytical and numerical models, to clearly identify areas that need further research and possible contact points between the different modeling domains (Technology TCAD, SPICE/Verilog-A standardization, advanced IC designs) . A freewheeling session will be also organized to review modeling activities of the CMC, NEEDS NanoHub and MOS-AK Groups.

Topics to be covered include the following:
  • Advances in semiconductor technologies and processing
  • Compact Modeling (CM) of the electron devices
  • Verilog-A language for CM standardization
  • New CM techniques and extraction software
  • CM of passive, active, sensors and actuators
  • Emerging Devices, CMOS and SOI-based memory cells
  • Microwave, RF device modeling, high voltage device modeling
  • Nanoscale CMOS devices and circuits
  • Technology R&D, DFY, DFT and IC Designs
  • Foundry/Fabless Interface Strategies
Speakers provisionary list (in alphabetic order)
  • Keith Green, TI, CMC Chair (US)
  • Benjamin Iniguez, URV (SP)
  • Eric Keiter, Xyce Team, Sandia (US) 
  • Luca Larcher, Uni. Modena (I)
  • Mark Lundstrom, NEEDS, NanoHub (US)
  • Michael Shur, RPI (US)
  • Sadayuki Yoshitomi, Toshiba (J)
In the terms of participation, intending participants and authors should also note the following dates: 
  • Call for Papers - Sept. 2013
  • 2nd Announcement - Oct 2013
  • Final Workshop Program - Nov. 2013
  • MOS-AK/GSA Workshop - Dec. 11, 2013

Further details and updates: <http://www.mos-ak.org/washington_dc_2013/
Email contact: <workshops@mos-ak.org

- with regards - WG (for the MOS-AK/GSA Committee
===
Arbeitskreis Modellierung von Systemen und Parameterextraktion 
Modeling of Systems and Parameter Extraction Working Group 
http://mos-ak.org/
===

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Aug 18, 2013

Semiconductor Device Characterization Engineer jobs

Indeed
Qualcomm  90 reviews - San Jose, CA
Interacts with other groups such as Design, Process, System, Reliability, and FA. 5+ years of related hands-on industrial experience....
Qualcomm - 5:25 AM
5+ years of related hands-on industrial design experience. Hands-on experience with device physics, device process, device characterization, and systems....
Qualcomm - 5:25 AM
IBM CORPORATION 1,821 reviews - Somers, NY
Possess working knowledge of semiconductor device development processes. Semiconductor Research and Development Process Improvement Engineer, IBM Corporation,...
New York Times - 8:27 AM

Aug 13, 2013

Fwd: 4 new Semiconductor Device Characterization Engineer jobs

Indeed

4 new jobs found
Knowledge of analog and mixed signal board level design including PCB layout guidelines a strong plus. Knowledge of both analog and digital video interface...
Intersil - 11:04 PM
GLOBALFOUNDRIES - Malta, NY
Technology related Bachelor's degree with 6 years experience ;. or Master's degree plus 5 years experience in process technology development area;....
GLOBALFOUNDRIES - 7:22 PM
Experience would be obtained through your educational level research and/or relevant job/internship experiences....
Intel - 2:45 PM
Quantum Solution - Sunnyvale, CA
Excellent proficiency of Cadence's custom IC design environment, analog/mixed signal circuit simulation (Spectre, Hspice, Ocean scripting, )....
Quantum Solution - 4:53 AM

Aug 8, 2013

[mos-ak] [Final Program] 11th MOS-AK ESSDERC ESSCIRC Workshop with the keynote speaker Larry Nagel

Together with Prof. Andrei Vladimirescu, R&D Scientific Coordinator, the Organizing Committee and Extended MOS-AK/GSA TPC Committee, we have pleasure to invite to the 11th consecutive MOS-AK ESSDERC ESSCIRC Workshop on Sept. 20, 2013 in Bucharest (RO). The event will open next decade of enabling compact modeling R&D exchange.  

The final workshop program as well as all further details and updates are on-line: <http://www.mos-ak.org/bucharest/

- with regards - WG (for the MOS-AK/GSA Committee

MOS-AK Workshop Program

 9:00 - 12:00Morning Session - Chair: Prof. Andrei Vladimirescu, ISEP (F); UCB (USA)
O_1 Welcome and Workshop Opening
W. Grabinski
MOS-AK Group (EU)
T_2 SPICE - MOS-AK Keynote
Larry Nagel
Omega Enterprises Consulting (USA)
T_3 NGSPICE: recent progresses and future plans
Paolo Nenzi*, Francesco Lannutti*, Robert Larice**, Holger Vogt**, Dietmar Warning**
*DIET - Sapienza University of Roma (I), ** NGSPICE Development Team
T_4 KCL and Linear/NonLinear Separation in NGSPICE
Francesco Lannutti
DIET - Sapienza University of Roma (I) and NGSPICE Development Team

Coffee Break
T_5 Modeling Junction Less FETs
Jean-Michel Sallese, Farzan Jazaeri, Lucian Barbut
EPFL (CH)
T_6 HiSIM-Compact Modeling Framework
Hans Juergen Mattausch
Uni. Hiroshima (J)
P_7 The Correct Account of Nonzero Differential Conductance in the Saturation Regime in the MOSFET Compact Model
Valentin Turin*, Gennady Zebrev**, Sergey Makarov***, Benjamin Iniguez****, and Michael Shur*****
*State University-ESPC (RU),**MEPHI (RU),***SYMICA Inc (RU),****URV (SP),*****RPI (USA)
12:00 -13:00
Lunch Break
13:00 -16:00
Afternoon Session - Chair: W. Grabinski, MOS-AK Group
T_8 State of the Art Modeling of Passive CMOS Components
Bernd Landgraf 
Infineon Technologies (A)
T_9 Compact I-V Model of Amorphous Oxide TFTs
Benjamin Iniguez*,Alejandra Castro-Carranza* , Muthupandian Cheralathan* , Slobodan Mijalkovic**, Pedro Barquinha***, Elvira Fortunato***, Rodrigo Martins***,Magali Estrada****, and Antonio Cerdeira****
*URV (SP), **Silvaco Ltd (UK), ***UNL(P), ****CINVESTAV (MEX)

Coffee Break
T_10 Three-Dimensional Electro-Thermal Circuit Model of Power Super-Junction MOSFET
Aleš Chvála, Daniel Donoval, Juraj Marek, Patrik Príbytný and Marián Molnár
Institute of Electronics and Photonics, Slovak University of Technology in Bratislava (SK)
T_11 A Close Comparison of Silicon and Silicon Carbide Double Gate JFETs
Matthias Bucher, Rupendra Sharma
Technical University of Crete, Chania, (GR)
T_12 Towards wide-frequency substrate model of advanced FDSOI MOSFET
Sergej Makovejev, Valeriya Kilchytska, Jean-Pierre Raskin, Denis Flandre
UCL (B)
16:00
End of the MOS-AK Workshop

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