Jan 16, 2013

New IC-CAP with GaN and Python support

Some news from EDN:


Agilent Technologies recently announced a new version of IC-CAP (integrated circuit characterization and analysis platform) for high-frequency device characterization and modeling, offering parameter extraction, data analysis, instrument control and interface responsiveness. This announcement actually includes two noteworthy topics: GaN and Python.

Angelov-GaN is an industry-standard compact device model for GaN semiconductor devices. Since GaN devices typically operate at high power, it is important to be able to model thermal issues and their impacts on device characteristics. Designers working with GaN quickly realized that GaAs models were not good enough. Fortunately, Prof. I. Angelov at Chalmers University of Technology developed his Angelov-GaN model as an alternative.

In its IC-CAP 2013.01, Agilent has fully embraced the Angelov model with the W8533 Angelov-GaN extraction package. An interface lets users execute a step-by-step extraction flow to obtain model parameters. A turnkey flow aims to provide a quick-start modeling of GaN devices. Roberto Tinti, device modeling product manager with Agilent EEsof EDA explained that the company developed the extraction package in conjunction with some Japanese and US GaN partners, but he was unable to reveal company names.

read more from the original...

ASP-DAC 2013 CALL FOR PARTICIPATION



Asia and South Pacific Design Automation Conference 2013

Pacifico Yokohama, Yokohama, JAPAN
January 22 - 25, 2013
http://www.aspdac.com/aspdac2013
WEB REGISTRATION DUE!!!: *** Jan. 17, 2013 ***
Please check the Registration Page:
For technical program, Please check the following link:

ASP-DAC 2013 is the eighteenth in a series of annual international conference on VLSI design automation. Asia and South Pacific region is one of the most active regions of design and fabrication of silicon chips in the world. The conference aims are providing the Asian and South Pacific CAD/DA and Design community with opportunities of interchanging ideas and collaboratively discussing the directions of the technologies related to all of Electronic Design Automation (EDA).

I N D E X [1] Keynote Speeches
[2] Designers' Forum
[3] Special Sessions
[4] Technical Sessions
[5] Tutorial
[1] Keynote Speeches
We have three keynote speakers from industry.
Keynote I : Wednesday, January 23, 8:30-10:00
"From Circuits to Cancer"
Dr. Sani Nassif, IBM
Keynote II : Thursday, January 24, 9:00-10:00
"Gearing Up for the Upcoming Technology Nodes"
Dr. Kee Sup Kim, Samsung Electronics
Keynote III : Friday, January 25, 9:00-10:00
"Human, Vehicle and Social Infrastructure System Development for
Sustainable Mobility - Development Innovation based on Large-Scale
Simulation -"
Dr. Hiroyuki Watanabe, Toyota Motor Corp.
[2] Designers' Forum
Designers' Forum is conceived as a unique program that shares the design experience and solutions of real product developments among LSI designers and EDA academia/developers. Admission fee is included in the Conference registration fee. Registration for Designers' Forum only is also available.

5A January 24, 13:40-15:40
Invited Talks: "Heterogeneous Devices and Multi-Dimensional Integration Design Technologies"
(Sony, Tokyo Inst. of Tech., TSMC, STARC, IMEC)
6A January 24, 16:00-18:00
Panel Discussion: "Future Direction and Trend of Embedded GPU"
(Panasonic, Kyushu Univ., ARM, Intel, Digital Media Professionals,
Fujitsu Lab.)
8A January 25, 13:40-15:40
Invited Talks: "Photonics for Embedded Systems"
(Hitachi, Luxtera, NEC, PETRA)
9A January 25, 16:00-18:00
Panel Discussion: "Harmonized Hardware-Software Co-design and Co-verification"
(STARC, Fujitsu Lab., Renesas, Tokyo Inst. of Tech., RWTH Aachen Cadence, Synopsys)

[3] Special Sessions
1D January 23, 10:20-12:20
University LSI Design Contest (Presentation + Poster Discussion)
21 designs are selected from 36 designs from five countries/areas.
1A January 23, 10:20-12:20
Invited Talks: "Advanced Modeling and Simulation Techniques for
Power/Signal Integrity in 3D Design"
(San Diego State Univ., Shizuoka Univ., KAIST, National Taiwan Univ.)
2A January 23, 13:40-15:40
Invited Talks: "Dependability of on-Chip Systems"
(Karlsruhe Inst. of Tech., Kyoto Univ., UC Irvine, UCLA)
3A January 23, 16:00-18:00
Invited Talks: "Design Automation for Flow-Based Microfluidic Biochips: Connecting Biochemistry to Electronic Design Automation"
(Ritsumeikan Univ., National Cheng Kung Univ., NAIST,
Tech. Univ. of Denmark, UC Riverside)
4A January 24, 10:20-12:20
Invited Talks: "High-Level Synthesis and Parallel Programming Models for FPGAs"
(Altera Toronto Technology Center, Advanced Digital Sciences Center,
Univ. of Illinois, Urbana-Champaign)
4D January 24, 10:20-12:20
Invited Talks: "Emerging Security Topics in Electronic Designs and Mobile Devices"
(Air Force Research Lab., New York Univ., UCLA, Univ. of Pittsburgh, Rutgers Univ.)
7A January 25, 10:20-12:20
Invited Talks: "Many-Core Architecture and Software Technology"
(Kyushu Univ., Univ. of Electro-Communications, Ritsumeikan Univ.,
Fixstars Corp., Fixstars Multicore Lab., TOPS Systems Corp.)
[4] Technical Sessions
97 papers are selected from 311 submissions for regular presentation
that cover key topics from system design to physical design. For
more details, please see the Home page:
http://www.aspdac.com/aspdac2013/technical_program/
[5] Tutorial
On January 22, five two-hour tutorials are scheduled, which will provide the audience with an introduction to hot topics in Embedded Multicore Programming, Pulse Based Design, Non-volatile System, Dependable Embedded Systems and RF-MEMs. Each tutorial will be presented twice a day to allow attendees to cover multiple topics. If you register for tutorials, you have the option to select three out of the five topics. Access to electronic files of tutorial presentations and a lunch coupon is included in Tutorial fee.

Tutorial-1 January 22, 9:30 - 11:30, 13:00 - 15:00
Programming Embedded Multiprocessor Systems: Application Code Mapping
and Performance Estimation Technologies
Tutorial-2 January 22, 9:30 - 11:30, 15:30 - 17:30
Pulse Based Design and Optimization
Tutorial-3 January 22, 13:00 - 15:00, 15:30 - 17:30
Temperature- and Process Variation-Aware Dependable Embedded Systems
Tutorial-4 January 22, 9:30 - 11:30, 13:00 - 15:00
Non-Volatile Memory Based Design
Tutorial-5 January 22, 13:00 - 15:00, 15:30 - 17:30
Introduction to RF CMOS and MEMS Design

Home page: http://www.aspdac.com
Sponsored by: ACM SIGDA, IEEE CASS, IEICE ESS, IPSJ SIGSLDM
Technical co-sponsor: IEEE CEDA
Japan Electronics Show Association(JESA)
1-1-3, Otemachi, Chiyoda-ku, Tokyo, 100-0004, Japan
Tel: 81-3-6212-5231 Fax: 81-3-6212-5225
E-mail: aspdac2013@aspdac.com


Jan 9, 2013

10th IWCM Workshop Program

10th International Workshop on Compact Modeling 

January 22 (Tue), 2013 

Pacifico Yokohama, Room 419

Yokohama, Japan

Time
#
Title
Authors
Affiliation
9:00-9:10

Opening: H. J.  Mattausch (Workshop Chair)




Power Devices   Chair: D. Navarro


9:10-9:30
1
HiSIM_HV Temperature Modeling for Multi-Geometry LDMOS: Comparison of the Temperature Flag Options
Y. Iino
Silvaco Japan
9:30-9:50
2
Analysis and Further Improvements of the Drain-Resistance Modeling in HiSIM_HV
T. Umeda et al.
Hiroshima University
9:50-10:10
3
Floating-Base Effect Modeling for IGBT Structure using Potential Modification
T. Yamamoto
et al.
Denso
10:10-10:30

- Break -




Novel FET Structures Chair: T. Nakagawa


10:30-10:50
4
Study on Dynamic Threshold Nanowire Tunnel FET
A. Zhang et al.
Peking University
Shenzhen
10:50-11:10
5
A DC Model of TFETs for SPICE Simulations
L. Zhang and M. Chan
HK UST 
11:10-11:30
6
A Surface Potential Based Compact Model of Organic Thin-Film Transistor for Circuit Simulation
T.K. Maiti et al.
Hiroshima University
11:30-11:40

-  Break -




Optical and Wireless Chair: J. He


11:40-12:00
7
An Embedded Modulation of Silicon Germanium FIN-LED - A simulation study
J. Kwon et al.
Seoul National
University
12:00-12:20
8
Predicting Key Parameters of Inductive Power Links
S. Raju et al.
HK UST 
12:20-14:00

- Lunch Break -




Aging and Degradation Chair: M. Miura-Mattausch


14:00-14:40
9
Invited Keynote: Interaction of Bloch Carrier and Bound State in the Reliability Modeling
Y.J. Park and
S. Choi
Seoul National
University
14:40-15:00
10
Development of Unified Predictive NBTI Model and its Application for Circuit Aging Simulation
C. Ma et al.
Hiroshima University, STARC
15:00-15:20
11
Effects of Nonlocal Concentration of Carriers in the Oxide for NBTI Simulation
S. Rhee et al.
Seoul National
University
15:20-15:40

-  Break -




Fabrication Variation Chair: Y. J. Park


15:40-16:00
12
Parameter Extraction for Statistical Variation of HV-MOSFETs
Y. Ueda et al.
Ricoh, STARC
16:00-16:20
13
Analysis of Gate-Length Dependence of MOSFET Random Variation by Using HiSIM-RP
S. Kumashiro
et al.
Renesas Electronics
16:20-16:40
14
Random Dopant Fluctuation Effects on Double Gate Tunneling FET Performance
Y. Zhu et al.
Peking University
Shenzhen
16:40-16:50

Closing: H.J. Mattausch (Workshop Chair)



Jan 7, 2013

IDESA Lecture


Lecture: MOSFET Modelling
J-M. Sallese; EPFL

Specific 90nm physical effects (DIBL, gate current, mobility saturation, velocity saturation). Available models and their RF performance: BSIM, EKV3, PSP. Modeling of analog and RF parameters (e.g., gm/ID, gm/gDS, CV modeling, gate leakage, etc.). Other topics include: noise modeling, distortion, breakdown effects, thermal issues and power devices, and physical layout effects (parasitics, test, maximizing gain-bandwidth, etc.). 

Location: STFC/RAL, UK; From: 14-Jan-2013 To: 18-Jan-2013
[more about IDESA Courses]

Job offer for Compact Modelling Engineer.

A job offer for compact modelling engineers, found in the web. For more information about the company, visit their website. Remember that we're not associated with them in any manner, and that we only post this as an information.

Compact Model Engineer
Reporting To: VP of Technology
Company: IO Semiconductor, Inc.
Location: San Diego, CA

Job Description and Responsibilities
  • Collaborate with product development, technology development and process engineering teams on the evaluation, optimization, validation, assessment and characterization of compact device models for circuit simulation.
  • Characterization and analysis of solid-state devices
  • Refinement and optimization of compact models for improved analog and RF
  • design efficiency and implementation on EDA platforms
  • DC and RF Spice model parameter sets for typical and skewed conditions
  • Device and circuit simulations
  • Test structure designs for parameter extractionReports, presentations and interpretations of simulation and characterization results

Required Skills and Experience
  • MS or PhD in electrical engineering, physics or equivalent
  • Solid technical understanding of semiconductor device physics, device
  • characterization and compact modelling for circuit simulation.
  • Experience with electrical characterization, including proficiency in setting-up
  • and programming measurement systems.
  • Programming experience in at least one high-level, script-based language, such as
  • HP Basic, Matlab or LabVIEW.
  • Experience in test structure design and layout.
  • Expertise in silicon-on-insulator (SOI) transistor physics and high speed device
  • characterization are highly desirable.
  • Experience with process and device simulation and modelling (TCAD) tools is
  • desirable.
  • Excellent verbal and written communication skills and a proven ability to work in
  • teams.
  • Excellent analytical skills
  • Excellent time management and organisational skills
  • A strong, hands-on individual contributor and a self-starter
  • Sound communication and interpersonal skills
  • Demonstrated ability to work effectively with others

Dec 20, 2012

[mos-ak] [on-line publications] 5th International MOS-AK/GSA Workshop in San Francisco, Dec. 12, 2012

The MOS-AK/GSA Working Group, a global compact modeling standardization forum, has delivered their 5th international compact modeling workshop, organized on Dec. 12, 2012 in the time frame of the IEDM Conference in San Francisco. The event was organized at swissnex receiving full sponsorship provided by leaders in electronic design automation including Agilent Technologies and Mentor Graphics. The FP7 COMMON Project, Eurotraining, and MOSIS Services were among the workshop technical program promoters. More than 40 international academic researchers and modeling engineers attended two sessions to hear 11 technical compact modeling talks. The session oral presentations are available for download at http://www.mos-ak.org/sanfrancisco_2012/

The compact modeling panel discussion moderated by Larry Nagel concluded the MOS-AK/GSA workshop. Invited international academic researchers and modeling engineers reviewed the status of compact modeling standardization and agreed that the Verilog-A standard offers a unique platform for compact model developments, validation, exchange and implementation into commercial as well as open source CAD/EDA tools. The panelists also pointed out the needs of further Verilog-A standard extensions and broader Verilog-AMS language definitions to better support compact device modeling, in particular focusing on Analog/RF noise applications. It is also expected that open source developers will actively contribute to standards promotion, addressing the challenges of related CAD/EDA software developments, such as Verilog-AMS debuggers supporting new model validations; and full featured, integral Verilog-AMS simulators for semiconductor device model benchmarking.

The MOS-AK/GSA Modeling Working Group coordinates several upcoming modeling events: a spring Q2/2013 MOS-AK/GSA meeting in Munich (D), followed by a special compact modeling session at the MIXDES Conference in Gdynia (PL); and an autumn Q3/2013 MOS-AK/GSA workshop in Bucharest (RO).

[read also recent press release]

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Dec 5, 2012

The 20nm Moore's Law Challenge - FinFET versus SOI technology... with John Chen, Nvidia

From Electronics weSRCH:

http://electronics.wesrch.com/weqEL1UYOB

Some say Moore's Law for semiconductors has stopped. But the world of 20nm technology is coming fast.  My guest, John Chen, Vice President, Wafer Foundry Group and Global Operations of Nvidia, was here to talk about it. He talks about the strengths and weaknesses of FinFET and SOI, including the power benefits and the design challenges.  Then we examine the question of Moore's Law slowing, followed up with the need for greater collaboration between fabless and foundry in a way that looks like a Virtual IDM.

The interview is in the original link, and it's quite interesting...