Job offers in LinkedIn

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Senior Research & Development Engineer
Group: Silicon Engineering Group
Location: Hyderabad, India
Contact @ akshat.kumar@synopsys.com

This position is for a senior R&D engineer who will join the TCAD team and work on the development and maintenance of state of the art back-end/interconnect analysis tools. Primary responsibilities include designing and developing physical models and numerical algorithms and implementing these algorithms in general purpose multidimensional semiconductor back-end/interconnect simulators in C++.
- PhD in a relevant field.
- Exp. with semiconductor back-end/ interconnect simulation tools focusing on one or, more of electrical, thermal, mechanical, and reliability analysis, numerical methods for solving partial differential equations (finite element and/or finite volume method), mesh generation.
- ~3 to 5 years of experience as a developer on large Finite Element Analysis simulators in either a commercial, or industrial/research lab setting. Prior experience with Synopsys TCAD tools is strongly preferred.
-Software development experience in C++ and preferably Tcl/Tk.
-Good communication skills and the ability to work within a team are essential.

some reading for summertime

Appl. Phys. Lett. 96, 253301 (2010); doi:10.1063/1.3453661 (3 pages)

Current bistability and carrier transport mechanisms of organic bistable devices based on hybrid Ag nanoparticle-polymethyl methacrylate polymer nanocomposites

Won Tae Kim, Jae Hun Jung, Tae Whan Kim, and Dong Ick Son

Abstract:The current bistability and the carrier transport mechanisms of organic bistable devices (OBDs) using Ag nanoparticle-polymethyl methacrylate (PMMA) nanocomposites have been investigated. Current-voltage measurements at 300 K on the Al/Ag nanoparticles embedded in the PMMA layer/indium-tin-oxide devices exhibit a current bistability with an ON/OFF ratio of 10³. Write-read-erase-read sequence results demonstrate the switching characteristics of the OBD. The cycling endurance number of the ON/OFF switching for the OBD is above 7×10⁴. The current bistability and carrier transport mechanisms of the OBD fabricated utilizing hybrid Ag nanoparticle-PMMA polymer nanocomposites are described on the basis of the experimental data.

 Physica E: Low-dimensional Systems and Nanostructures

Quantum transport modeling of defected graphene nanoribbons 

 I. Deretzis, G. Fiori, G. Iannaccone, G. Piccitto and A. La Magna


Abstract: We study backscattering phenomena during conduction for graphene nanoribbons of μm lengths, from single vacancy scatterers up to finite defect concentrations. Using ab initio calibrated Hamiltonian models we highlight the importance of confinement and geometry on the shaping of the local density of states around the defects that can lead to important alterations on the transport process, giving rise to impuritylike conduction gaps in the conductance distribution. Within a statistical analysis of finite defect concentration we show that conductance degradation can become very important.




 Solid-State Electronics
The spatial origin of current noise in semiconductor devices in the framework of semiclassical transport
C.E. Kormana, B.A. Noaman

Abstract: A new model to semiconductor device electronic noise is presented in the framework of semiclassical transport theory. The salient feature of this model is that it connects the current noise characteristics directly to the physics of scattering of the semiclassical transport theory and makes no additional assumption regarding the nature of noise. Employing this approach, this work investigates the spatial origin of the current noise across two semiconductor structures. In this approach the terminal current noise is directly related to carrier scattering inside the device, which is accounted for in the Boltzmann transport equation (BTE), without the need to add Langevin noise terms to the calculations. Accordingly, it utilizes the well-established spherical harmonics expansion (SHE) technique to solve the BTE, and it combines analytical and numerical methods, in contrast with the Monte Carlo (MC) approach that employs ensemble averages of randomly generated events. The model leads to the solution of a time-dependent transient solution of the BTE with special initial and Ohmic boundary conditions that is solved in the frequency domain to directly compute the terminal current noise spectral density. It is also shown that with this approach the Nyquist theorem under thermal equilibrium conditions is recovered.

 

The Ten Commandments for Effective Standards

The Ten Commandments for Effective Standards:

Practical Insights for Creating Technical Standards

Karen Bartleson (Author)

Publisher: Synopsys Press (May 7, 2010)
Language: English
ISBN-10: 1617300020
ISBN-13: 978-1617300028

About the Author:
Karen Bartleson has three decades' experience in the computer chip industry. She is known for her work in the area of standards for electronic design automation, and is also one of the pioneers into social media in her industry, including Twitter. She is the author of "The Standards Game," a blog focused on the standards arena. Karen holds a BSEE from California Polytechnic State University, San Luis Obispo, California, and was the recipient of the Marie R. Pistilli Women in Design Automation Achievement Award in 2002. Her Twitter handle is @karenbartleson. --This text refers to the Paperback edition.

MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Seville on Sept. 17, 2010 // 2nd announcement

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MOS-AK/GSA ESSDERC/ESSCIRC Workshop: http://www.mos-ak.org/seville/
"Frontiers of the Compact Modeling for Advanced Analog/RF Applications"

The MOS-AK/GSA Workshop in Seville will be organized as an integral
part of the ESSDERC/ESSCIRC Conference. The MOS-AK/GSA Workshop is
HiTech forum to discuss the frontiers of the electron devices modeling
with emphasis on simulation-aware models. Original papers presenting
new developments and advances in the compact/spice modeling and its
Verilog-A standardization are solicited. Suggested topics include (but
are not limited to):
   * Compact Modeling (CM) of the electron devices
   * Verilog-A language for CM standardization
   * New CM techniques and extraction software
   * CM of passive, active, sensors and actuators
   * Emerging Devices, CMOS and SOI-based memory cells
   * Microwave, RF device modeling, high voltage device modeling
   * Nanoscale CMOS devices and circuits
   * Technology R&D, DFY, DFT and IC Designs
   * Foundry/Fabless Interface Strategies
On-line abstract submission is open with the deadline on July 15, 2010
http://mos-ak.org/seville/abstracts.php

Tentative list of the invited speakers (alphabetic order):
   * Raphael Clerc, MINATEC: Compact modeling of nanoscale MOSFETs:
beyond the drift diffusion approximation
   * Gilles Depeyrot, Dolphin Integration: Verilog-A Compact Model
Standardization
   * Tibor Grasser, TU Wien: Recent Developments in Device
Reliability Modeling
   * Benjamin Iniguez, URV: Advances in Multigate MOSFET Modeling
   * David Jimenez, UAB: Analytic surface potential and drain current
model for negative capacitance FETs
   * Bernabé Linares-Barranco, NMC: The EKV/ACM compact models for
mismatch modeling down to 90nm and for new emergent non-CMOS
nanotechnology FETs
   * Josef Watts, IBM: Modeling Standardization: Enabling the
worldwide design community
   * Sadayuki Yoshitomi, Toshiba: Device Level RF IC Design

Further details and updates: http://www.mos-ak.org/seville/
==========================================================
* Wroclaw: June 24-26 www.mixdes.org/Special_sessions.htm
* Tarragona: June.31-July.1  http://www.compactmodelling.eu/tc_programme.php
* Seville: Sept. 17  http://www.mos-ak.org/seville/
* California: Dec'2010 http://www.mos-ak.org/
==========================================================

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To post to this group, send email to mos-ak@googlegroups.com.
To unsubscribe from this group, send email to mos-ak+unsubscribe@googlegroups.com.

For more options, visit this group at http://groups.google.com/group/mos-ak?hl=en.

[mos-ak] MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Seville on Sept. 17, 2010 // 2nd announcement

MOS-AK/GSA ESSDERC/ESSCIRC Workshop: http://www.mos-ak.org/seville/
"Frontiers of the Compact Modeling for Advanced Analog/RF
Applications"

The MOS-AK/GSA Workshop in Seville will be organized as an integral
part of the ESSDERC/ESSCIRC Conference. The MOS-AK/GSA Workshop is
HiTech forum to discuss the frontiers of the electron devices modeling
with emphasis on simulation-aware models. Original papers presenting
new developments and advances in the compact/spice modeling and its
Verilog-A standardization are solicited. Suggested topics include (but
are not limited to):
* Compact Modeling (CM) of the electron devices
* Verilog-A language for CM standardization
* New CM techniques and extraction software
* CM of passive, active, sensors and actuators
* Emerging Devices, CMOS and SOI-based memory cells
* Microwave, RF device modeling, high voltage device modeling
* Nanoscale CMOS devices and circuits
* Technology R&D, DFY, DFT and IC Designs
* Foundry/Fabless Interface Strategies
On-line abstract submission is open with the deadline on July 15, 2010
http://mos-ak.org/seville/abstracts.php

Tentative list of the invited speakers (alphabetic order):
* Raphael Clerc, MINATEC: Compact modeling of nanoscale MOSFETs:
beyond the drift diffusion approximation
* Gilles Depeyrot, Dolphin Integration: Verilog-A Compact Model
Standardization
* Tibor Grasser, TU Wien: Recent Developments in Device
Reliability Modeling
* Benjamin Iniguez, URV: Advances in Multigate MOSFET Modeling
* David Jimenez, UAB: Analytic surface potential and drain current
model for negative capacitance FETs
* Bernabé Linares-Barranco, NMC: The EKV/ACM compact models for
mismatch modeling down to 90nm and for new emergent non-CMOS
nanotechnology FETs
* Josef Watts, IBM: Modeling Standardization: Enabling the
worldwide design community
* Sadayuki Yoshitomi, Toshiba: Device Level RF IC Design

Further details and updates: http://www.mos-ak.org/seville/
==========================================================
* Wroclaw: June 24-26 www.mixdes.org/Special_sessions.htm
* Tarragona: June.31-July.1 http://www.compactmodelling.eu/tc_programme.php
* Seville: Sept. 17 http://www.mos-ak.org/seville/
* California: Dec'2010 http://www.mos-ak.org/
==========================================================

--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To post to this group, send email to mos-ak@googlegroups.com.
To unsubscribe from this group, send email to mos-ak+unsubscribe@googlegroups.com.
For more options, visit this group at http://groups.google.com/group/mos-ak?hl=en.

SPICE update from Mentor

Daniel Payne talked with See-Mei Chan, Technical Marketing Manager at Mentor Friday morning because they couldn’t connect in Anaheim earlier this week. Daniel wanted to better understand what is new with Eldo, the SPICE circuit simulator at Mentor.

Read more in June 18th, 2010 post by Daniel Payne in Analog Fast SPICE, DAC 2010, Fast SPICE, SPICE circuit simulation.

News and Views: Nature Nanotechnology

A. M. Ionescu

Electronic devices: Nanowire transistors made easy

Nature Nanotechnology, vol. 5, iss. 3, pp. 178 – 179, March 2010

Figure (a) A junction FET is turned on in the (strong) inversion condition, when a channel of minority carriers is formed just under the gate, and junction barriers to their flow are reduced. The off state of the junction FET corresponds to high junction barriers and the suppression of the inversion channel. The horizontal red line shows the bottom of the depletion region, and the slanted red lines indicate the limits of the depletion region controlled by the gate. (b) In contrast, the on state of a junctionless FET is obtained in 'flat band' conditions, with majority carriers travelling through a highly doped film. The device (which requires a thin-film silicon-on-insulator substrate) turns off when the gate-controlled depletion extends over the whole film. Both devices operate with the source grounded and a positive potential applied to the drain. Vt denotes the threshold voltage (positive for the n-type devices). Similar descriptions apply to the operation of complementary p-type FETs. Blue and red colours depict electron and hole doping respectively, with a darker colour indicating heavier doping. The white regions correspond to the depletion regions, and the green colour represents the gate oxide.

References

1. Lilienfeld, J. E. Method and apparatus for controlling electric current. US patent 1,745,175 (1925)
2. Shan, Y., Ashok, S. & Fonash, S. J. Appl. Phys. Lett. 91, 093518 (2007)
3. Lin, Y.-W., Marek-Sadowska, M., Maly, W., Pfitzner, A. & Kasprowicz, D. in Int. Conf. Computer Design 557–562 (IEEE, 2008)
4. Soree, B. & Magnus, W. in 10th Int. Conf. Ultimate Integration of Silicon 245–248 (IEEE, 2009)
5. Lee, C. W. et al. Appl. Phys. Lett. 94, 053511 (2009)
6. Colinge, J. P. et al. Nature Nanotech. 5, 225–229 (2010)
7. Tsutsui, K. et al. in Int. Workshop Nano CMOS 56–68 (IEEE, 2006)
8. Aoyama, T. et al. in Int. Workshop Junction Technol. 110–115 (IEEE, 2009)