The European (7th Framework Programme) Call for Postdoctoral Individual Marie Curie Fellowships is open until August 18 2009.
I am looking for one or two candidates to work in my research group at the Universitat Rovira i Virgili (Tarragona, Spain) in the field of compact modeling of advanced semiconductor devices. Therefore, I would like to receive CVs from potential applicants. Once I have selected the candidates, we will make the application.
The candidates must have a Ph D in Electrical Engineering, Electronic Engineering, Physics or Telecommunication Engineering.
There are two open Calls: the one for Intra European Fellowships (FP7-PEOPLE-2009-IEF) and the one for International Incoming Fellowships (FP7-PEOPLE-2009-IIF). Therefore, candidates from European countries can apply for an Intra European Fellowship and candidates from outside Europe can apply for an International Incoming Fellowship.
These felowships can be for one or two years. Salaries are extremely good and the prestige of having this type of fellowship is very high. For this reason, there is a tough competition to get these fellowships.
I am looking for candidates for these Marie Curie Grants, both from Europe and outside Europe. Candidates must have a good CV (preferably with more than 4 publications in international journals, in order to have chances). In order to fit the Marie Curie requirements, their age should be below 35.
If successful, the postdoctoral researchers will work on the characterization of compact modeling of any of the advanced semiconductor devices targeted by our research European projects: nanoscale MOSFETs, SOI and Multi-Gate MOSFETs, strained-Si/SiGe MOSFETs, Schottky-Barrier MOSFETs, nanowire FETs, III-V HEMTs and organic TFTs.
The specific device/s in which the postdoctoral researcher will work will depend on his/her preference and background.
Candidates must send me by e-mail (to benjamin.iniguez@gmail.com) a CV or resume by AUGUST 6. Successful applicants will be informed by August 7, and then we will start to make the application. The successful candidates will be informed on the steps to do.
Tarragona is a small city (110000 inhabitants) on the Mediterranean coast, about 100 Km south from Barcelona, and very well connected to Barcelona and the main Spanish cities by rail and highway. Tarragona is a very old city, very important during the Roman Empire, and with a lot of historical landmarks.
The quality of life in Tarragona is excellent. Mediterranean and mild climate the whole year. Wonderful beaches around the city (even at the city). Mountains close to the city (even the Pyrenees are not far). Besides, the city is very quiet, but with an intense nightlife.
My research group in the Department of Electronic Engineering, Universitat Rovira i Virgili (URV) is one of the strongest groups in compact modeling in Europe. We are leading one European project on compact modeling (in which a total of 15 European universities and companies participate). We also participate on two other European projects (one about nanoscale MOSFETs and another one about organic Thin Film Transistors).
I am looking forward to receiving excellent applications!
Benjamin Iñiguez
Department of Electronic Engineering
Tarragona, SPAIN
Universitat Rovira i Virgili (URV)
E-mail: benjamin.iniguez@gmail.com
Jul 24, 2009
Papers in IEEE TED, Vol 56 (8), Aug. 2009
Jul 22, 2009
SINANO-NANOSIL Workshop
The SINANO-NANOSIL Workshop will take place in Athens on September 18th, 2008, during the ESSDERC-ESSCIRC Conference.
This Workshop, continuation of the former SINANO Workshop, is a very valuable discussion forum in the area of nanoelectronics devices.
The aim of this Workshop is to present the status and trends of CMOS and beyond-CMOS nanodevices for terascale ICs and to establish a discussion forum in the field of nanoelectronics devices.
The SINANO-NANOSIL Workshop is supported by the SINANO Institute, which is a new European entity created by the main laboratories of the European academic community working in nanoelectronics, and by the European Network of Excellence NANOSIL which targets Silicon-based Nanodevices and is funded by the European Commission for the 7th Framework Programme, from 2008 to 2011. The former SINANO Workshop was funded by the prebvious Network of Excellence, called SINANO.
The program of the SINANO-NANOSIL Workshop consists of several presentations given by a number of representatives of NANOSIL partners:
9:00 Limitations in future gate stack materials
O. Engstrom
Chalmers University
9:30 Metallic source/drain for advanced MOS architectures: from material engineering to device integration
E. Dubois,
IEMN
10:00 Coffee break
10:30 Advanced Memory devices using multi-gate and 3D structures
B. DeSalvo
LETI
11:00 Tunnel FET or Ferroelectric FET to achieve a sub-60mV/decade small swing switch
A. Ionescu
EPFL
11:30 Electron Transport in Graphene Quantum Dots and Quantum Point Contacts
L. Ponomarenko
University of Manchester
12:00 Lunch
13:30 Variability in Nanoscale CMOS and Nanowires
A. Asenov
University of Glasgow
14:00 Simulation of gate leakage currents in UTB MOSFETs and Nanowires
A. Schenk,
ETH-Zentrum
14:30 3D quantum transport simulations of Si Nanowires: impact of elastic and inelastic scattering
M. Pala
IMEP-LAHC, Grenoble INP-Minatec
15:00 Deterministic solution of the 1D Boltzmann transport equation
G. Baccarani, E. Gnani, A. Gnudi and S. Reggiani
ARCES-IUNET
15:30 End of the Workshop
This Workshop, continuation of the former SINANO Workshop, is a very valuable discussion forum in the area of nanoelectronics devices.
The aim of this Workshop is to present the status and trends of CMOS and beyond-CMOS nanodevices for terascale ICs and to establish a discussion forum in the field of nanoelectronics devices.
The SINANO-NANOSIL Workshop is supported by the SINANO Institute, which is a new European entity created by the main laboratories of the European academic community working in nanoelectronics, and by the European Network of Excellence NANOSIL which targets Silicon-based Nanodevices and is funded by the European Commission for the 7th Framework Programme, from 2008 to 2011. The former SINANO Workshop was funded by the prebvious Network of Excellence, called SINANO.
The program of the SINANO-NANOSIL Workshop consists of several presentations given by a number of representatives of NANOSIL partners:
9:00 Limitations in future gate stack materials
O. Engstrom
Chalmers University
9:30 Metallic source/drain for advanced MOS architectures: from material engineering to device integration
E. Dubois,
IEMN
10:00 Coffee break
10:30 Advanced Memory devices using multi-gate and 3D structures
B. DeSalvo
LETI
11:00 Tunnel FET or Ferroelectric FET to achieve a sub-60mV/decade small swing switch
A. Ionescu
EPFL
11:30 Electron Transport in Graphene Quantum Dots and Quantum Point Contacts
L. Ponomarenko
University of Manchester
12:00 Lunch
13:30 Variability in Nanoscale CMOS and Nanowires
A. Asenov
University of Glasgow
14:00 Simulation of gate leakage currents in UTB MOSFETs and Nanowires
A. Schenk,
ETH-Zentrum
14:30 3D quantum transport simulations of Si Nanowires: impact of elastic and inelastic scattering
M. Pala
IMEP-LAHC, Grenoble INP-Minatec
15:00 Deterministic solution of the 1D Boltzmann transport equation
G. Baccarani, E. Gnani, A. Gnudi and S. Reggiani
ARCES-IUNET
15:30 End of the Workshop
9:00 Limitations in future gate stack materials
O. Engstrom
Chalmers University
9:30 Metallic source/drain for advanced MOS architectures: from material engineering to device integration
E. Dubois,
IEMN
10:00 Coffee break
10:30 Advanced Memory devices using multi-gate and 3D structures
B. DeSalvo
LETI
11:00 Tunnel FET or Ferroelectric FET to achieve a sub-60mV/decade small swing switch
A. Ionescu
EPFL
11:30 Electron Transport in Graphene Quantum Dots and Quantum Point Contacts
L. Ponomarenko
University of Manchester
12:00 Lunch
13:30 Variability in Nanoscale CMOS and Nanowires
A. Asenov
University of Glasgow
14:00 Simulation of gate leakage currents in UTB MOSFETs and Nanowires
A. Schenk,
ETH-Zentrum
14:30 3D quantum transport simulations of Si Nanowires: impact of elastic and inelastic scattering
M. Pala
IMEP-LAHC, Grenoble INP-Minatec
15:00 Deterministic solution of the 1D Boltzmann transport equation
G. Baccarani, E. Gnani, A. Gnudi and S. Reggiani
ARCES-IUNET
15:30 End of the Workshop
O. Engstrom
Chalmers University
9:30 Metallic source/drain for advanced MOS architectures: from material engineering to device integration
E. Dubois,
IEMN
10:00 Coffee break
10:30 Advanced Memory devices using multi-gate and 3D structures
B. DeSalvo
LETI
11:00 Tunnel FET or Ferroelectric FET to achieve a sub-60mV/decade small swing switch
A. Ionescu
EPFL
11:30 Electron Transport in Graphene Quantum Dots and Quantum Point Contacts
L. Ponomarenko
University of Manchester
12:00 Lunch
13:30 Variability in Nanoscale CMOS and Nanowires
A. Asenov
University of Glasgow
14:00 Simulation of gate leakage currents in UTB MOSFETs and Nanowires
A. Schenk,
ETH-Zentrum
14:30 3D quantum transport simulations of Si Nanowires: impact of elastic and inelastic scattering
M. Pala
IMEP-LAHC, Grenoble INP-Minatec
15:00 Deterministic solution of the 1D Boltzmann transport equation
G. Baccarani, E. Gnani, A. Gnudi and S. Reggiani
ARCES-IUNET
15:30 End of the Workshop
ESSCIRC/ESSDERC early registration deadline ***26/7/2009***
Some information from Matthias Bucher
Dear Colleagues,
Please let me draw your attention to the deadline for early registration for ESSDERC/ESSCIRC 2009 in Athens, 14-18/9/2009, is this Sunday, 26 July. For those who have not registered yet, consider the reduced registration fees, http://www.esscirc2009.org/?pid=3.
I also would like to draw your attention to the Tutorials on Monday 14/9/2009, http://www.esscirc2009.org/?pid=7. Of course you are aware the MOS-AK workshop is held on Friday 18/9/2009, please **do** register as well! (even though it is free, and even for those of you who might not attend ESSDERC/ESSCIRC).
As an additional information, I’m attaching below some links to hotels that you might want to consider booking, in the Acropolis and Plaka region, about 20-25 minutes (either metro and/or walking) or 15 minutes by taxi, from the Caravel hotel where the conference is held. Hotels very close to the Caravel are probably already booked (those indicated on the conference site) or very expensive (Hilton, and Caravel). Don't delay booking, I hope these are of some help.
Acropolis Museum Boutique hotel, 48 Sygrou Ave., 11720 Athens
http://www.booking.com/hotel/gr/acropolis-museum-boutique.en.html?sid=86c27c055ff3d2b31320a517ff769305
Airotel Parthenon, 6 Makri Str., 11742 Athens
http://www.booking.com/hotel/gr/parthenon.en.html?sid=86c27c055ff3d2b31320a517ff769305
Acropolis Select Hotel, 37-39 Falirou Str., 11742 Athens
http://www.tripadvisor.com/Hotel_Review-g189400-d230390-Reviews-Acropolis_Select_Hotel-Athens_Attica.html
or hotels in the "Plaka" area (again close to Acropolis and close to metro stations)
Amazon Hotel, Mitropoleos 19 & Pentelis 7, 10557 Athens
http://www.booking.com/hotel/gr/amazonathens.html
PLAKA HOTEL ATHENS, 7 Kapnikareas & Mitropoleos, Athens
http://www.holiday-in-athens.com/athens/plaka-hotel-athens.html
Jul 17, 2009
Post-Silicon Solutions Emerging
Post-Silicon Solutions Emerging:
Researchers have an array of new technologies in the pipeline to boost CMOS logic and memory performance, Sematech Vice President Raj Jammy said Tuesday at the Device Scaling TechXPOT at SEMICON West. High-mobility graphene channels, gates built around nanowires, finFETs with III-V materials -- all promise to blow past the power/performance capabilities of silicon CMOS.
David Lammers, News Editor -- Semiconductor International, 7/15/2009
Researchers have an array of new technologies in the pipeline to boost CMOS logic and memory performance, Sematech Vice President Raj Jammy said Tuesday at the Device Scaling TechXPOT at SEMICON West.
 |
| "We need disruptive materials and technologies," said Raj Jammy of Sematech. |
High-mobility graphene channels, gates built around nanowires, finFETs with III-V materials -- all promise to blow past the power/performance capabilities of silicon CMOS. Jammy, in charge of materials and emerging technologies research at Sematech, warned that "people entrenched in the silicon world" may need to rethink as scaling of today's CMOS transistors becomes increasingly difficult.
"We need disruptive materials and technologies," Jammy said, describing R&D progress on several post-22 nm options. Progress is being made on heterogeneous devices, where germanium is used as the channel in the pFET and indium gallium arsenide (InGaAs), for example, on the nFET. Nanowires with a gate-all-around design are drawing more R&D attention, and work continues on finFETs -- vertical structures that allow better control of the channel.
Memory R&D is equally vibrant. For decades, mainstream memories have been based on charge storage. "But when you make these devices really small, charge storage is no longer possible." On the horizon are phase change memories (PCRAMs) and metallic resistive RAMs (ReRAMs), though Jammy acknowledged that the question regarding ReRAM technology is: "Does it work at less than 20 nm?"
Also under study are zero-leakage nanoelectrical-mechanical system (NEMS) devices, which Jammy said "exhibit instant on and off." And because they are mechanical, they can safely operate in hazardous environments, such as a nuclear power plant.
 |
| Schubert Chu of Applied Materials spoke of the potential of carbon-doped silicon for nFET strain. |
Schubert Chu, an Applied Materials product manager for epi/LPCVD products, examined the possibility of embedded silicon carbon (eSiC) being used to enhance the performance of the nFET. While embedded silicon germanium (eSiGe) has served to effectively strain the pFET, SiC has been a tougher challenge, largely because the carbon atoms tend to move around.
Chu said that an AMD-led team has shown a 30% improvement with nFETs strained by SiC structures. "Silicon carbon is on track to be adopted at the 22 nm generation."
SiGe stressors face challenges as the germanium content moves from 25-30% at the 45 nm node to >40% at the 22 nm node. Applied Materials has developed a "Siconi" pre-clean option for its Centura epitaxial deposition tool, which Chu said will extend epi strain technologies.
Jammy said the industry faces serious cost challenges. "When we hear that it may cost $80M for a EUV scanner, we are not going in the right direction on costs," he said.
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