May 29, 2009

Agilent-EEsof X-Parameters Course

Agilent-EEsof is offering an 3-day course – July 7-9 (Massy – France)

WHAT WILL YOU LEARN?
  • This course starts with an overview of non-linear components behavioral modeling and the extension of S-parameters into X-parameters.
  • Then it drives you through the calibration requirements for X-parameters measurements. Finally the use of X-parameters models in ADS (Advanced Design System) is illustrated with cascaded amplifiers in an LTE (3rd Gen. Partnership Project - Long Term Evolution) RF subsystem.
  • Participants will have the opportunity to drive the measurements and perform hands-on exercises in the ADS software.

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Organic, Molecular and Nanostructured Electronics - Physics and Technology

Date: June 8-12, 2009 | Continuing Education Units

Description: This course will review basic concepts underlying the design, fabrication, and operation of three dominant types of organic electronic devices: light emitting devices (OLEDs), photosensitive devices (solar cells and photodetectors), and field effect transistors (OFETs). We will also discuss, but devote less time to, organic lasers, organic memories, and chemical sensors. The course aims to present a broad and practical survey of the field and to immerse you in the broad field of organic materials. As a sub-class of nanostructured solids, organic thin films exemplify challenges of the practical nanotechnologies. Many concepts presented in the class are directly transferable to a broader field of nanostructured materials.

Instructors: Professors Vladimir Bulovic and Marc Baldo of the MIT Laboratory of Organic Optics and Electronics.

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International Summer School MOMiNE 2009

International Summer School on Modelling and Optimization in Micro- and Nano- Electronics - MOMiNE Italy Sept. 2009: The aim of the School is to stimulate intensive transfer of knowledge and discussion on modeling and optimization of electronic circuits and devices, by presenting the latest developments, insights, methods, algorithms and ideas in these areas of research, providing also indications for future research directions. An important aspect is the involvement of researchers working for industries, which can provide a more timely indication of the most relevant up-to-date problems encountered in real industrial environments.

The International Summer School MOMINE 2009 will be held from 31/08 to 12/09 at:

Grand Hotel San Michele
Località: Bosco 8/9, 87022 Cetraro (Cosenza), Italy
Phone: (+39) 0982 91012 Fax: (+39) 0982 91430

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May 28, 2009

Graduate Student Meeting on Electronic Engineering

The Graduated Student Meeting on Electronic Engineering (formerly Nanoelectronics and Photonics Systems Workshop), has been an annual event, created and organized by the Universitat Rovira i Virgili (URV), in Tarragona (Catalonia, Spain) since 2003. It consists of two days of plenary talks given by invited prestigious researchers (from different countries) about selected topics related to electronic engineering and two poster sessions were PhD students in this field will present their work.

This Graduated Student Meeting has become a very useful forum for PhD students and researchers in the field of Electronic Engineering. The present edition will take place in June 19th and 20th.

This year, the Graduated Student Meeting is being sponsored by the NANOSIL European Network of Excellence.

Awards for the best student paper/posters in two categories: one category for Master students and another category for Doctoral Students.

2-pages abstracts corresponding to paper or poster presentations and plenary talks will be published in the Proceedings. The deadline for abstracts reception is June 8th.

The plenary talks will be given by the following lecturers:

Prof Juin J Liou.
University of Central Florida, Orlando, FL (USA). "Protecting Microchips agains Electrostatic Discharge (ESD) Shock."

Dr Michele Penza.
Italian Agency for New Technologies, Energy and Environment.
Department of Physical technologies and new materials. Research Center Brindisi (Italy). "Carbon nanotube gas sensors: chemiresistors and SAW devices."

Prof. Ettore Napoli. Department of Electronic and Telecommunication Engineering. University of Naples Federico II (Italy). "Superjunction power devices".

Dr Denis Buttard. CEA-GrenobleLaboratoire de Silicium Nanoélectronique Photonique et StructuresINAC/SP2M/SiNaPSMINATEC-BCA. 38054 Grenoble Cedex 9 (France). "Elaboration and structural investigation of the confined growth of silicon nanowires in a nanoporous matrix: application to phovoltaic cell".

Prof. Yuhua Cheng. Shanghai Research Institute of Microelectronics, Peking University (China). "Design-for-Manufacturing in Nano-CMOS Era."

Dr. Daniela Iacopino. Nanotechnology Group. Tyndall National Institute. Cork (Ireland).
"Nanocrystal-Molecule Nanostructures: Formation, Plasmonic Properties & Electrical Contacting"

Tarragona is located in the south of Catalonia, in the northeast corner of the Iberian Peninsula.
Tarraco (the Roman name for Tarragona) was one of the most important cities in the Roman Empire. On 30 November 2000, the UNESCO committee officially declared the Roman archaeological complex of Tàrraco a World Heritage Site. This recognition is intended to help ensure the conservation of the monuments, as well as to introduce them to the broader international public.

In June the weather is warm enough to go to the beaches in or around Tarragona, but comfortable enough to walk and do sightseeing in the city. Thanks to its Mediterranean climate, its clean beaches with fine and gloden sand, and its singular artistic and architectural heritage, Tarragona is one of the most important tourism hubs in Europe.

I encourage Ph D students to send abstracts and attend this interesting Meeting!

Job offer in Compact Modelling - 28 May 2009

I post here a job offer from LinkedIn, I think it may be of interest for many of you, dearest readers.... Please remember that we only copy here the offer, and that we are not related in any way to those offering the position!!
In case you are interested, kindly pass your CV immediately to gopal.svks@gmail.com / gopal@svcircuit.com

Senior Manager/Manager -Analog-RF,AMS–Malaysia
Exp-PhD / Master with 10+ , candidate should be solid in Analog,RF characterization, SPICE & compact modeling for high voltage MOS, BJT, BCD devices

Placement location –Malaysia
Position -- very urgent and need to be filled ASAP.
Interview - 2weeks altogether.
Package – Will be the best in the semiconductor industry
Type -Full time and permanent with our client..


Malaysia Responsibilities:
• Lead a team of engineers to provide Integrated Circuit Design Technology solutions.
• Supervise test-chip design for "Client" technology characterization, SPICE model generation
for RF, Analog and mixed signal active and passive devices, and development of process design
kit (PDK) for "Client" technologies.
• Review, update, and manage electrical design rule (EDR) specifications for all "Client"
technologies – accuracy and availability of up-to-date revision.
• Interface with "Client" technology development (TD), customer engineering (CE), and Fab
engineering departments to support technology development, customer support, and
manufacturing, respectively.
• Interact with marketing group to provide modeling solutions to "Client" customers.
• Follow and comply with the procedures and by-laws of "Client" Environmental Management
System (EMS).
• Review all environmental objectives, targets, and plans and ensure their implementation in
accordance to the requirements set by "Client" EMS.
Requirements:
• 10+ years of experience in managing integrated circuit Design Technology including design rule
generation, device characterization and compact modeling and industry best practices.
• Extensive knowledge of compact modeling for Analog/RF and mixed-signal technologies
including high voltage MOS, BJT, BCD devices for circuit simulation.
• Extensive knowledge of integrated passive and active components characterization and modeling.
• Good verbal/written communication skills and proven ability to work in and lead cross functional
teams.
• Proven leadership and management skills in high technology industry.
• M.S. or PhD in Electrical Engineering, Physics, or related technical fields with > 10 years relevant
experience in logic, Analog/RF, and mixed-signal device & interconnect modeling as well as CAD
to support customer design.
• Working experience in TCAD device design is added advantage

May 26, 2009

Engineers Discover Fundamental Flaw In Transistor Noise?

I copy here a part of a post in EDN (follow the link to get the full story... be aware that this seems to be quite yellowish press!!!):

According to the engineers at the National Institute of Standards and Technology (NIST) who discovered the problem, it will soon stand in the way of creating more efficient, lower-powered devices like cell phones and pacemakers unless we solve it.

While exploring transistor behavior, the team found evidence that a widely accepted model explaining errors caused by electronic "noise" in the switches does not fit the facts. A transistor must be made from highly purified materials to function; defects in these materials, like rocks in a stream, can divert the flow of electricity and cause the device to malfunction. This, in turn, makes it appear to fluctuate erratically between "on" and "off" states. For decades, the engineering community has largely accepted a theoretical model that identifies these defects and helps guide designers' efforts to mitigate them.

Those days are ending, says NIST's Jason Campbell, who has studied the fluctuations between on-off states in progressively smaller transistors. The theory, known as the elastic tunneling model, predicts that as transistors shrink, the fluctuations should correspondingly increase in frequency.

However, Campbell's group at NIST has shown that even in nanometer-sized transistors, the fluctuation frequency remains the same. "This implies that the theory explaining the effect must be wrong," Campbell said. "The model was a good working theory when transistors were large, but our observations clearly indicate that it's incorrect at the smaller nanoscale regimes where industry is headed."

The findings have particular implications for the low-power transistors currently in demand in the latest high-tech consumer technology, such as laptop computers. Low-power transistors are coveted because using them on chips would allow devices to run longer on less power—think cell phones that can run for a week on a single charge or pacemakers that operate for a decade without changing the battery. But Campbell says that the fluctuations his group observed grow even more pronounced as the power decreased. "This is a real bottleneck in our development of transistors for low-power applications," he says. "We have to understand the problem before we can fix it—and troublingly, we don't know what's actually happening."

Campbell, who credits NIST colleague K.P. Cheung for first noticing the possibility of trouble with the theory, presented* some of the group's findings at an industry conference on May 19, 2009, in Austin, Texas. Researchers from the University of Maryland College Park and Rutgers University also contributed to the study.


May 24, 2009

Students from Microelectronics Students’ Group win Cadence® Contest

CADENCE® EMEA (Europe, Middle East and Africa regions) organized the first full custom design contest, entitled Virtuoso Olympics. In this unique and innovative event the best layout designers from the top academic institutions in Europe will compete for the title of Fastest full custom layout designer of the year.

Two students from the Microelectronics Students’ Group of the University of Porto (FEUP) won this Cadence® contest. Daniel Oliveira and Américo Dias accepted the challenge and accomplished the target, wining the first place.